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Search Results: 1 - 10 of 461888 matches for " A.Chilambuchelvan "
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Harmonic Analysis of Distributed PV System Under High and Low Irradiance
International Journal of Engineering and Technology , 2010,
Abstract: This paper presents a unique modelling of harmonics and comparison between high irradiance and low irradiance in PV system connected to a grid. The signals used are actual tested waveforms in a distributed PV system. The percentage error has been calculated for the individual parameters in both cases. The comparative study using Chirp Z transform (CZT) with 7 term B Harris Window will enable to model harmonics using this algorithm in the future. The paper shows the performance of the method proposed in different measurement conditions.
Modelling and Analysis of DFIG Wind Turbine Harmonics Generated in Grids
International Journal of Engineering and Technology , 2010,
Abstract: In this paper an analytic technique for modelling harmonics is proposed for a DFIG wind turbine connected to the grid. An algorithm based on Hilbert transform for the analysis of harmonics in power systems isdeveloped. The simulation results prove the effectiveness of the Hilbert Transform (HT) for power harmonic analysis in DFIG wind turbine connected to a grid.
International Journal of Engineering Sciences and Emerging Technologies , 2013,
Abstract: In today’s world, World Wide Web is the most popular information providers. A website is a collection of web pages and Web pages usually include information for the users. The web sites are designed with common templates and content. The template is used to access the content easily by consistent structures even the templates are not explicitly announced. The current Template extraction techniques are degrading the performance of web applications such as search engine due to irrelevant terms in templates.In this work, we present new method for extracting templates from a large number of web documents which are generated from heterogeneous templates. This paper cluster the web documents based on the similarity of underlying template structures in the documents so that the template for each cluster is extracted simultaneously.
A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation
Usha Bhanu.N,A.Chilambuchelvan
International Journal of VLSI Design & Communication Systems , 2012,
Abstract: Evaluating the previous work is an important part of developing new hardware efficient methods for theimplementation of DWT through Lifting schemes. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The architectures are represented in terms of parallel filter, row column, folded, flipping and recursive structures. The methods for scanning of images are the line-based and the block-based and their characteristics for the given application are given. The various architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes.
Neural Network Based Normalized Fusion Approaches for Optimized Multimodal Biometric Authentication Algorithm  [PDF]
E. Sujatha, A. Chilambuchelvan
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.78103
Abstract: A multimodal biometric system is applied to recognize individuals for authentication using neural networks. In this paper multimodal biometric algorithm is designed by integrating iris, finger vein, palm print and face biometric traits. Normalized score level fusion approach is applied and optimized, encoded for matching decision. It is a multilevel wavelet, phase based fusion algorithm. This robust multimodal biometric algorithm increases the security level, accuracy, reduces memory size and equal error rate and eliminates unimodal biometric algorithm vulnerabilities.
An Approach for Content Retrieval from Web Pages Using Clustering Techniques  [PDF]
R. Manjula, A. Chilambuchelvan
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.79230
Abstract: Mining the content from an information database provides challenging solutions to the industry experts and researchers, due to the overcrowded information in huge data. In web searching, the information retrieved is not an appropriate, because it gives ambiguous information for the user query, and the user cannot get relevant information within the stipulated time. To overcome these issues, we propose a new methodology for information retrieval EPCRR by providing the top most exact information to the user, by using the collaborative clustered automated filter which makes use of the collaborative data set and filter works on the prediction by providing the highest ranking for the exact data retrieved. The retrieval works on the basis of recommendation of data which consists of relevant data set with highest priority from the cluster of data which is on high usage. In this work, we make use of the automated wrapper which works similar to the meta crawler functionality and it obtains the content in the semantic usage data format. Obtained information from the user to the agent will be ranked based on the Enabled Pile clustered data with respect to the metadata information from the agent and end-user. The information is given to the end-user with the top most ranking data within the stipulated time and the remaining top information will be moved to the data repository for future use. The data collected will remain stable based on the user preference and works on the intelligence system approach in which the user can choose any information under any instances and can be provided with suitable high range of exact content. In this approach, we find that the proposed algorithm has produced better results than existing work and it costs less online computation time.
GSTP: Geographic Secured Two Phase Routing Using MD5 Algorithm  [PDF]
B. Prathusha Laxmi, A. Chilambuchelvan
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.78159
Abstract: Secured Two Phase Geographic Greedy Forwarding (SecuTPGF) is a geographic greedy forwarding?protocol for transmitting multimedia data stream in Wireless Multimedia Sensor Networks?(WMSN) in a secure and reliable manner. Cryptographic and MAC authentication mechanisms are used to implement security for both node and message authentication. In this paper, a modified?version of SecuTPGF, the GSTP routing provides security for both node and message authentication by using MD5 algorithm with a reduced computation power. In SecuTPGF, two different algorithms are used for node and message authentication, and GSTP routing uses “MD5Algorithm” for both node and message authentication. Using MD5 algorithm for node and message authentication, the average number of transmission paths increased and average number of hops used for transmission decreased when compared to the?SecuTPGF. By conducting security analysis & evaluation experiments, the effectiveness of GSTP routing algorithm is proved.
Investigation and Simulation of Phase to Ground Fault in DFIG based Wind Turbine System
B. BabyPriya,A. Chilambuchelvan
Bonfring International Journal of Power Systems and Integrated Circuits , 2011,
Abstract: With advent of wind farms in large scale and capacity continuously increasing, issues related to performance of the overall system needs to be addressed. Faults produced by wind turbine generator systems will impact not only the wind farms but also the interconnected system. In this paper the modeling of a 6MW wind farm using doubly fed induction generator is described and the effects of phase to ground faults under various load conditions are studied. For the study use phasor control of the Doubly Fed Induction Generator is used.
Novel NoC Topology Construction for High-Performance Communications
P. Ezhumalai,A. Chilambuchelvan,C. Arun
Journal of Computer Networks and Communications , 2011, DOI: 10.1155/2011/405697
Abstract: Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation. 1. Introduction The integration of several heterogeneous components into a single system gives rise to new challenges. With the change of dramatic improvement in this area, it is essential to have an adaptable communication facility that can cope up with the versatile programming of the cores. Such systems will have to process data in real time, perform data transfer at the rate of hundreds of Tbps, support multiple functions and protocols for communications with standard wired and wireless interface, provide security and secrecy and cope up with time-to-market (TTM) pressures and so. Existing SoCs’ communications are based on dedicated wires and shared bus (single/hierarchical) having various constraints. Dedicated wires do not provide flexibility for communication needed for hardware platforms and cannot cope up the increased number of cores. Due to exclusive access of shared bus its utilization is as low as 10%. This is inflexible to parameters required supporting heterogeneous components of SoC and not scalable. Global synchronization is not possible with this technique. It has very high signaling delay per unit length. Reduction in SNR and signal integrity and increase in cross-talk occur with the increase in parasitic capacitance and resistor as bus wire length increases. To achieve the above-mentioned requirements and to overcome the above-mentioned problems the use of a network-centric approach, that is, network-on-chip (NoC), which is globally asynchronous and locally
RETRACTED: An Improved Fuzzy Based Algorithm for Detecting Text from Images Using Stroke Width Transform  [PDF]
Angamuthu Thilagavathy, Arulgnanaprakasam Chilambuchelvan
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.74031

Short Retraction Notice

This article has been retracted to straighten the academic record. In making this decision the Editorial Board follows COPE's Retraction Guidelines. The aim is to promote the circulation of scientific research by offering an ideal research publication platform with due consideration of internationally accepted standards on publication ethics. The Editorial Board would like to extend its sincere apologies for any inconvenience this retraction may have caused.

The full retraction notice in PDF is preceding the original paper, which is marked \"RETRACTED\".

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