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Search Results: 1 - 10 of 27464 matches for " Very High Speed Integrated Description Language (VHDL). "
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Real-Time System: Fire and Smoking Control System (Case Study)
Muhammed Ali Suliman Mesleh,Mohammed Ashraf Zoghoul
World of Computer Science and Information Technology Journal , 2013,
Abstract: A real-time system is software where the correct functioning of the system depends on the results produced by the system and the time at which these results are produced. The main objective of this study is to show the importance of real-time system as an application that uses computer system in the human life. Since it helps to control vital and dangerous aspects, that otherwise can not be controlled.The motivation for this study is to avoid fire occurrence and smoking habits in certain places. Since by using this system the place and time of event can be determined in short period. For that reason, the need for using real-system raised.
vhdl-c++翻译器设计与实现
吴清平?,刘明业?
软件学报 , 2002,
Abstract: vhdl(vhsic(veryhighspeedintegratedcircuit)hardwaredescriptionlanguage)是描述数字系统的硬件描述语言,c++是编写顺序语句程序的高级编程语言.vhdl编译型模拟器需要采用具有顺序特征的c++语句表征具有并发特征的vhdl电路设计.提出了一种面向对象的vhdl-c++翻译方法,充分利用了这两种语言的面向对象的特征,采用c++类来描述vhdl的实体、结构体及进程等元素,并通过一个c++模拟调度核心完成了用顺序语句描述并发电路的工作.通过此方法可将vhdl源描述转化为功能等价的c++代码,并在模拟调度核心的调度下,使用顺序语句模拟出数字系统并发功能,完成编译型模拟器的构造,实现vhdl的高速模拟.用这种翻译方法翻译出来的c++代码具有结构清晰、可扩充性强的特点,与模拟核心形成的编译型模拟器的模拟速度相比,解释型模拟器速度有较大提高.该方法已在模拟系统中得以成功应用.最后给出了部分试验结果,进一步说明了算法的效率和优点.
Implementation of FPGA based PID Controller for DC Motor Speed Control System
Prashant Kumar# 1 , Ravi Mishra
International Journal of Engineering Trends and Technology , 2013,
Abstract: In this paper, the implementation of software module using 'VHDL' for Xilinx FPGA (XC2S30) based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.1i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where, the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed
High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier  [PDF]
S. Jayakumar, Dr. A. Sumathi
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.711312
Abstract: In this, todays world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay; area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.
Secure Transmission of Biometric Scan Images Using Data Encryption Standards(DES) Algorithm
Computer Science and Engineering , 2012, DOI: 10.5923/j.computer.20120205.04
Abstract: Biometric Scan Images, however, is vulnerable to unauthorized access while in storage and during transmission over a network. Unauthorized user can make a fake copy from image file from memory device or computer. Biometric Data in form of images are very confidential information of user. If they are in unauthorized hand then misuse of data may be harmful to authorized user. As in case of Unique ID each and every citizen of country have their Biometric scan images of finger, face and thumb and Iris all in original form like JPEG,JPG,GIF,PNG,BMP etc. To protect them from unauthorized access we can encrypt images so they can’t be detected and used. Protection is required at very initial end so that images can be directly saved in form of encrypted image in memory device. First image will be converted into pixels. Each pixel will be converted into DataStream and stored in codebook in same order as of pixels in image. Digitized pixels will have a group of data bits and each pixels or set of pixels will be encrypted using DES algorithm. The whole Programming and design can be done in any platform like MATLAB, C, C++, Xilinx ISE 13.4 Software. The advantage of using Xilinx is that in this platform we can design a Layout of it so that finally a Chip level Solution can be provided.
A Study and Analysis of High Speed Adders in Power-Constrained Environment
Vivek Kumar,Vrinda Gupta,Rohit Maurya
International Journal of Soft Computing & Engineering , 2012,
Abstract: An overview of the performance of 1-bit full adder in different CMOS logic styles and in depth examination of the advantages and limitations of each of them with respect of speed and power dissipation are presented. Ten 1-bit full adder circuit based on these logic styles are chosen for the extensive evaluation. These circuits were redesigned at the transistor-level in tsmc 0.18 μm technology and comparison reported here uses Mentor Graphics ELDO simulations to assess their performance. The hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The work presented in this paper gives a quantitative comparison of the adder cell performance.
Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
Subodh Wairya,Rajendra Kumar Nagaria,Sudarshan Tiwari
International Journal of VLSI Design & Communication Systems , 2012,
Abstract: This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and powerdelay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
Grounding Impedance Measurement of High Speed Railway Integrated Grounding System  [PDF]
Zhang Yi, Jianguo Wang, Yadong Fan, Mi Zhou, Li Cai
Journal of Power and Energy Engineering (JPEE) , 2015, DOI: 10.4236/jpee.2015.34027
Abstract:

The high-speed railway integrated grounding system is the basic guarantee for the safe and stable operation of the railway. It is the world’s largest long-distance horizontally elongated joint grounding system, which stretches the length of hundreds to thousands of kilometers, and its structure is not only different from power station and substation grounding system, but also different from the transmission line tower, lightning rod and other small grounding devices. There is little research information on the grounding impedance of high-speed railway integrated grounding system. This paper adopted 0.618 compensation method and reverse away method respectively, measured a section of high-speed railway integrated grounding system grounding impedance by JD16 and CA6425. Measurement results are in good agreement using those two type instrument. By using 0.618 compensation method, the measurement result will be gradually converged at 0.3 Ω with the increasing of current electrode distance, which is the real grounding impedance of integrated grounding system. By using reverse away method, the maximum measurement result difference is less than 0.024 Ω with the lead of current electrode distance increasing. The measurement results will be rapidly converged 0.25 Ω. The results showed that the reverse away method is helpful to shorten the length of current electrode wiring. The measurement error will be small when the current electrode wiring is longer.

Undergraduate Curriculum Development for Digital Integrated Circuit Design  [PDF]
Xin Chen
Creative Education (CE) , 2012, DOI: 10.4236/ce.2012.326128
Abstract: This article describes the development of a Digital Integrated Circuit Design curriculum, which includes how to select the design level and how to implement the design. The curriculum is for the undergraduates in grade four, whose major is microelectronics. The development is in the background of very large scale integrated circuits. Since the popular design flow is a hierarchy of abstraction levels, the goal of the curriculum is to develop the students’ ability to design an actual circuit from scratch. Comparison is provided from two aspects. The first aspect is the contents of various published textbooks. The second aspect is the contents of similar courses in famous universities.
Boundary Induced Inductive Delay in Transmission of Electromagnetic Signals  [PDF]
Yong Yang, Mingzhi Li, Yan Sun, Dongfei Pei, Shengyong Xu
Journal of Electromagnetic Analysis and Applications (JEMAA) , 2012, DOI: 10.4236/jemaa.2012.44020
Abstract: When an electromagnetic signal transmits through a coaxial cable, it propagates at speed determined by the dielectrics of insulator between the cooper core wire and the metallic shield. However, we demonstrate here that, once the shielding layer of the coaxial cable is cut into two parts leaving a small gap, while the copper core wire is still perfectly connected, a remarkable transmission delay immediately appears in the system. We have revealed by both computational simulation and experiments that, when the gap spacing between two parts of the shielding layer is small, this delay is mostly determined by the overall geometrical parameters of the conductive boundary which connects two parts of the cut shielding layer. A reduced analytic formula for the transmission delay related with geometrical parameters, which is based on an inductive model of the transmission system, matches well with the fitted formula of the simulated delay. This above structure is analog to the situation that an interconnect is between two inter-modules in a circuit. The results suggest that for high speed circuits and systems, parasitic inductance should be taken into full consideration, and compact conductive packaging is favorable for reducing transmission delay of inter-modules, therefore enhancing the performance of the system.
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