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A digital background calibration
technique that corrects the capacitor mismatches error is proposed for
successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC
which is based on tri-level switching. The termination capacitor in the
Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the
digital weights of all other unit capacitors are corrected with respect to the
reference capacitor. To make a comparison between the size of the unit
capacitor and that of the reference capacitor, each input sample is quantized
twice. The unit capacitor being calibrated is swapped with the reference
capacitor during the second conversion. The difference between the two
conversion results is used to correct the digital weight of the unit capacitor
under calibration. The calibration technique with two reference capacitors is
presented to reduce the number of parameters to be estimated. Behavior simulation
is performed to verify the proposed calibration technique by using a 12-bit SAR
ADC with 3% random capacitor mismatch. The simulation results show that the
Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range
(SFDR) is improved from 60.0 dB to 85.4 dB.
In wireless sensor networks, the
traditional multi-relay incremental cooperative relaying (MIR) scheme could
improve the system throughput over the fading channel enormously by exploiting
multiple relay nodes to retransmit the copy of the source packet to the
destination in turn, but increase the energy consumption and transmission delay.
In order to mitigating the energy consumption and transmission delay, this
paper proposes a new cooperative relaying scheme termed as
incremental-selective relaying with best-relay selection (ISR), which selects
the best relay node from the candidate relays to retransmit the packet to the
destination only when the direct transmission between the source and the
destination is not successful. Expressions of normalized throughput, normalized
delay and energy efficiency for the ISR and MIR systems are derived respectively
and their performances are compared through simulations. The results show that
normalized throughput, normalized delay and energy efficiency for the ISR
system all outperform the corresponding performances of the MIR system.
Especially, there are different the optimal number of relays which can maximize
the energy efficiency of system.
This paper proposes a digital
background calibration scheme for timing skew in time-interleaved
analog-to-digital converters (TIADCs). It detects the relevant timing error by
subtracting the output difference with the sum of the first derivative of the
digital output. The least-mean-square (LMS) loop is exploited to compensate the
timing skew. Since the calibration scheme depends on the digital output, all
timing skew sources can be calibrated and the main ADC is maintained. The
proposed scheme is effective within the entire frequency range of 0 ? fs/2.
Compared with traditional calibration schemes, the proposed approach is more
feasible and consumes significantly lesser power and smaller area.