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Search Results: 1 - 10 of 4038 matches for " Leakage Current "
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A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits  [PDF]
Tarun Kumar Gupta, Kavita Khare
Circuits and Systems (CS) , 2013, DOI: 10.4236/cs.2013.42028
Abstract:

A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25and 110temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.

Simulation Suggests Origin of Potential Induced Degradation of Solar Cell  [PDF]
Masato Ohmukai, Akira Tsuyoshi
Journal of Power and Energy Engineering (JPEE) , 2017, DOI: 10.4236/jpee.2017.56004
Abstract: Solar cells are well known as devices for sustainable electric energy generation. Nowadays the potential induced degradation has been brought up as an obstacle problem for practical use. In order to determine the cause of this kind of degradation, numerical simulation by a finite difference time domain method has been performed for computational electromagnetics in the case that the thunder attacks the solar modules. The results show that the dielectric breakdown in the glass covered over the solar cells triggered by the thunderstroke is critical. So it is helpful to protect the dielectric breakdown in the glass from the thunderstroke.
Effect of Parameters on Potential Induced Degradation of Solar Cell  [PDF]
Masato Ohmukai, Akira Tsuyoshi
Journal of Power and Energy Engineering (JPEE) , 2017, DOI: 10.4236/jpee.2017.56003
Abstract: Solar cells are widely used to generate electric energy even at homes. It surely has a great advantage of sustainability. However, the potential induced degradation has been found to be an obstacle problem for practical use. It was reported that the main cause is the dielectric breakdown in the glass covered over the solar cells triggered by the thunderstroke. In this paper, the effects of the parameters such as the position of thunderstroke, the wave form, the peak value and the front duration of the lightning current, were examined by means of numerical calculation. For the lightning current, a step-like waveform and an impulse waveform were examined. The effect of the induced voltage was found to be independent of the waveform. The peak value, the front duration of the lightning current greatly affects the induced voltage.
Study of the Structural and Electrical Properties of Cr-Doped BiFeO3 Ceramic  [PDF]
S. S. Arafat, S. Ibrahim
Materials Sciences and Applications (MSA) , 2017, DOI: 10.4236/msa.2017.810051
Abstract: Multiferroic BiFe1-xCrxO3 (x = 0.2 and 0.4) ceramics were synthesized in a single phase. The effects of Cr3+ substitution on the crystal structure, dielectric permittivity and leakage current were investigated. Preliminary X-ray structural studies revealed that the samples had a rhombohedral perovskite crystal structure. The dielectric constant ε' significantly increased while the dielectric loss tanδ was substantially decreased with the increase in Cr3+ substitution. The temperature effect on the dielectric properties exhibited an anomaly corresponding to magneto-electric coupling in the samples and was shifted to lower temperatures with the increase in Cr3+ substitution. The leakage current density also reduced in magnitude with the increase in the Cr3+ substitution.
Gate Leakage Current in GaN HEMT’s: A Degradation Modeling Approach
Electrical and Electronic Engineering , 2012, DOI: 10.5923/j.eee.20120206.09
Abstract: In this paper we present an empirical preliminary model able to simulate the degradation with time in the gate leakage current in GaN HEMT devices. The model is based on extensive reverse and forward current measurements, carried out on a wide range of different device designs and under different bias, performed over aged transistors by III-V Lab (Alcatel-Thales) within the European KORRIGAN. A closed form expression for the reverse gate current, depending on time, as well as the expression parameters extraction procedure are presented. The experimental and simulated results presented illustrate the validity of the model as well as it’s usefulness in reliability studies.
Analyze of Hydrophobic Characteristic of Surface Material Based on The Value of THD Leakage Current
Abdul Syakur,Hermawan,Sarjiya,Hamzah Berahim
TELKOMNIKA , 2009,
Abstract: Polymer material has been developed to replace the porcelain insulator material and glass. When it is used as outdoor insulator, environmental conditions have a significant influence to the value of surface discharge current, especially for the coastal area and industry. Salt, dust and chemicals contaminant are suspected as the causes of initial current of surface discharge and the insulator surface degradation which lead to a flashover. To analyze the performance of the insulator surface when the leakage current occurs, the Total Harmonic Distortion (THD) is needed to be determined. The value of THD leakage current indicates the hydrophobic characteristic of surface material. This paper analyzes the results of leakage current measurement in laboratory-scale based on IEC 587:1986 with Inclined-Plane Tracking (IPT) method to the High Density Polyethylene (HDPE) polymer material which is provided in smooth and rough surface. The testing voltage is 50 Hz AC. Data of leakage current magnitude values cover its maximum average as a function of time and the result of FFT to the wave form of the leakage current. As the result, the value of percentage THD decrease as the function of time. The smooth surface material has THD value 43.42% and the rough surface has 15.89%.
Power Optimization Technique for Pulsed Latches
P.Sreenivasulu,Dr. K.Srinivasa Rao,J.I.R Prakash
International Journal of Soft Computing & Engineering , 2013,
Abstract: In this paper, we implement a design technique forregisters used in pulsed latches in order to make leakage currentlow thus reducing standby power consumption. This is made byconsidering short or long timing path and launching or capturingregister. In this work each register trades clock-to-Q delaymaintaining the same timing constraints, setup time and hold timemaintaining clock-to-Q delay constant for reducing the leakagecurrent by developing three different dual threshold voltageregisters. The overall reduction in the leakage current of a registercan exceed 90% while maintaining the clock frequency and otherdesign parameters such as area and dynamic power the same.This work presents an elegant methodology using pulsed latchinstead of flip-flop without altering the existing design style. Itreduces the dynamic power of the clock network, which canconsume half of a chip's dynamic power. Real designs have shownapproximately a 20 percent reduction in dynamic power using thebelow methodology. Three ISCAS 89 benchmark circuits areutilized to evaluate the methodology, demonstrating, on average,23% reduction in the overall leakage current. The overallreduction in leakage current is compared for each case indifferent technologies. Predictive device models are used for eachtechnology. The analysis is performed using H-SPICE.
Designing a Full Adder Circuit Based on Quasi-Floating Gate  [PDF]
Sahar Bonakdarpour, Farhad Razaghian
Energy and Power Engineering (EPE) , 2013, DOI: 10.4236/epe.2013.53B012
Abstract:

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

A SVM Based Condition Monitoring of Transmission Line Insulators Using PMU for Smart Grid Environment  [PDF]
Kailasam Saranya, Chinnusamy Muniraj
Journal of Power and Energy Engineering (JPEE) , 2016, DOI: 10.4236/jpee.2016.43005
Abstract: A new methodology for the detection and identification of insulator arc faults for the smart grid environment based on phasor angle measurements is presented in this study and the real time phase angle data are collected using Phasor Measurement Units (PMU). Detection of insulator arcing faults is based on feature extraction and frequency component analysis. The proposed methodology pertains to the identification of various stages of insulator arcing faults in transmission lines network based on leakage current, frequency characteristics and synchronous phasor measurements of voltage. The methodology is evaluated for IEEE 14 standard bus system by modeling the PMU and insulator arc faults using MATLAB/Simulink. The classification of insulator arcs is done using Support Vector Machine (SVM) technique to avoid empirical risk. The proposed methodology using phasor angle measurements employing PMU is used for fault detection/classification of insulator arcing which further helps in efficient protection of the system and its stable operation. In addition, the methodology is suitable for wide area condition monitoring of smart grid rather than end to end transmission lines.
Metodología de Evaluación de los Pararrayos de Carburo de Silicio
Kanashiro,Arnaldo G; Zanotti Jr,Milton; Obase,Paulo F; Bacega,Wilson R;
Información tecnológica , 2010, DOI: 10.4067/S0718-07642010000300013
Abstract: this work presents results of a research project dveloped for determining the diagnostic of silicon carbide surge arresters. tests were performed in these arresters in the laboratory, considering the power frequency spark-over voltage and lightning spark-over voltage tests. the results were compared with values of leakage current, radio-influence voltage test and thermovision, obtained in the same surge arresters. it was observed a reasonable correlation between high values of the leakage current, considering the amplitude and the third harmonic component, and the presence of degradation in the surge arresters. therefore, it was concluded that leakage current measurements can provide important information about the stage of degradation of the surge arresters. measurements in the substations during several years could provide the identification, in case of leakage current variations, of deteriorated silicon carbide surge arresters.
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