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A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.
Since in designing the full adder circuits, full adders
have been generally taken into account, so as in this paper it has been
attempted to represent a full adder cell with a significant efficiency of
power, speed and leakage current levels. For this objective, a comparison
between five full adder circuits has been provided. Applying floating gate
technology and refresh circuits in the full adder cell lead to the reduction of
leakage current on the gate node. The simulations were accomplished in this
paper, through HSPICE software and 65 nm CMOS technology. The simulation
results indicate the considerable efficiency of power consumption, speed and
leakage current in the full adder cell rather than other cells.