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Search Results: 1 - 10 of 3165 matches for " Fault "
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Comprehensive Modulation and Classification of Faults and Analysis Their Effect in DC Side of Photovoltaic System  [PDF]
Mehrdad Davarifar, Abdelhamid Rabhi, Ahmed El Hajjaji
Energy and Power Engineering (EPE) , 2013, DOI: 10.4236/epe.2013.54B045
Abstract: The first step in automatic supervision, condition monitoring and fault detection of photovoltaic system is recognition, exploration and classification of all possible faults that maybe happen in the system. This paper aims to perceive, classified, simulate and discus all electrical faults in DC side of photovoltaic system, regarding electrical voltage and current inspections. For that, simplified hybrid model of photovoltaic panel in MATLAB environment is used. Investigation and classification of each type of faults is down and the effects of the faults are illustrated in this paper. Flash test are applied to improved electrical model. Current-Voltage curves signature are interpreted and investigated in simulation environment.
Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression  [PDF]
Nuno Guerreiro, Marcelino Santos, Paulo Teixeira
Circuits and Systems (CS) , 2013, DOI: 10.4236/cs.2013.45054
Abstract:

Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

Transient and Permanent Fault Injection in VHDL Description of Digital Circuits  [PDF]
Parag K. Lala
Circuits and Systems (CS) , 2012, DOI: 10.4236/cs.2012.32026
Abstract: The ability to evaluate the testability of digital circuits before they are actually implemented is critical for designing highly reliable systems. This feature enables designers to verify the fault detection capability of online as well as offline testable digital circuits for both permanent and transient faults, during the design stage of the circuits. This paper presents a technique for transient and permanent fault injection at the VHDL level description of both combinational and sequential digital circuits. Access to all VHDL blocks a system is straight forward using a specially designed single fault injection block. This capability of inserting transient and permanent faults should help in evaluating the testability of a digital system before it is actually implemented.
High Impedance Fault Detection of Distribution Network by Phasor Measurement Units  [PDF]
Mohsen Ghalei Monfared Zanjani, Hossein Kazemi Karegar, Hasan Ashrafi Niaki, Mina Ghalei Monfared Zanjani
Smart Grid and Renewable Energy (SGRE) , 2013, DOI: 10.4236/sgre.2013.43036
Abstract: This paper proposes a new algorithm for High Impedance Fault (HIF) detection using Phasor Measurement Unit (PMU). This type of faults is difficult to detect by over current protection relays because of low fault current. In this paper, an index based on phasors change is proposed for HIF detection. The phasors are measured by PMU to obtain the square summation of errors. Two types of data are used for error calculation. The first one is sampled data and the second one is estimated data. But this index is not enough to declare presence of a HIF. Therefore another index introduces in order to distinguish the load switching from HIF. Second index utilizes 3rd harmonic current angle because this number of harmonic has a special behaviour during HIF. The verification of the proposed method is done by different simulation cases in EMTP/MATLAB.
Fault Location Method and Simulation Analysis of Parallel Compensating Capacitors  [PDF]
Daquan Du, Na Zheng, Zhiming Su
Energy and Power Engineering (EPE) , 2013, DOI: 10.4236/epe.2013.54B111
Abstract:

At present, the operational parallel compensating capacitors can only through the protection action for the information, so we can‘t location the fault capacitor. In order to obtain every parallel capacitor running status information and meanwhile according to internal structure and the operation mode of film capacitor, this paper established the physical model on the single capacitor and the capacitors and simulated different forms of capacitor fault model and calculated currents changes which flow through the capacitor in every group. According to the above situation, we established fault criterion matrix of capacitors. The simulation results show that the fault criterion matrix can reflect capacitor running state information accurately, and it positioned fault capacitor effectively.

5 Analysis of Fault-Related Folding in South of Birjand  [PDF]
Mohammad Khalaj
Open Journal of Geology (OJG) , 2015, DOI: 10.4236/ojg.2015.56037
Abstract: Folds have a significant development in the Cretaceous-Tertiary rock units of the northern part of Bagheran Mountains in southwest Birjand between Lut and Sistan structural zones. The general trends of fold axis and axial surface are E-W and the folds are less exposed by distance from mountain and plain boundary. Geometric and kinematic status investigation of folds (such as f2 fold in the middle part) and faults shows that faulting process has created some of the folds leading to their development. Such structures are described as fault-related folds. Also, analysis of geometry and mechanism of faults indicate that back thrusts have the largest influence on generation and development of folds in this region.
Fault Diagnosis Technology Based on Model Driven  [PDF]
Xie Zhang, Zufeng Xu, Jun Wu
World Journal of Engineering and Technology (WJET) , 2015, DOI: 10.4236/wjet.2015.33C035
Abstract:

Fault diagnosis is an important application of the power grids monitoring system. Under the situation of continuous development of smart grid, it brings new challenges to the fault diagnosis technology. A fault diagnosis expert system based on model driven approach is proposed in this paper. And the corresponding fault modeling technology based on Fault Logic Description Language (FLDL) is described step by step. Practices show that this system could meet the requirements of processing fault alarm information rapidly and reliably by operator.

Structural Style in the Zagros Fold-Thrust Belt: The Gavbast Anticline, Coastal Fars  [PDF]
Hadi Vaseghi, Zahra Maleki, Mehran Arian
Open Journal of Geology (OJG) , 2016, DOI: 10.4236/ojg.2016.62011
Abstract: The Gavbast anticline is located in the Coastal Fars area of the Zagros folded belt, with north-south trend. The study anticline is restricted to the Bavush and Paskhand anticlines from North, the Gezzeh and Dehnow anticlines from South, the Varavi anticline from West and Nakh anticline from East (Figure 1). Description of fold geometry is important because they allow comparisons within and between folds and pattern-recognition in addition to occurrence and distribution of fold systems. The main goal of this paper is to define folding style of the Gavbast anticline and define structural features affected on them in the study area. In this research, we used the Tectonics FP software, Global Mapper software and geological maps and reports of Iranian National Oil Company. In addition, we used common classification of fold for indicating of folding mechanism of the Tabnak anticlinal structure. In the Gavbast anticline, fold style elements in all parts of this anticline have been calculated and analyzed for indicating of folding style mechanism. The results of this method have been shown the folding geometry changes accurately. The Gavbast anticline is gentle in structural sections D-D' and G-G' to K-K'. The anticline is an open fold in the L-L'?section. Also fold type in the E-E' and F-F' sections of the Gavbast anticline is steeply inclined sub-horizontal. These sections are located between the Razak (western part) and Hendurabi fault (eastern part). It seems that E-E' and F-F' parts in the Gavbast anticline have been suffered most deformation affected by the Razak and Hendurabi faults. At the end of, it seems that, the Razak and Hendurabi faults have major effects on folding style. This structure is a very good sample for effect of strike slip faults on the folding geometry and for this reason; the Gavbast anticline is considered a special structural style in the Zagros fold-thrust Belt.
On the Production Testing of Memristor Ratioed Logic (MRL) Gates  [PDF]
Ahmed Shukry Emara, Ahmed Hassan Madian, Hassanein Hamed Amer, Sherif Hassanein Amer, Mohamed Bakr Abdelhalim
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.710257
Abstract: This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is afamily that uses memristors along with CMOS inverters to design logic gates. Two-input NAND andNOR gates are investigated using the stuckat fault model for the memristors and the five-faultmodel for the transistors. Test escapes may take place while testing faults in the memristors.Therefore, two solutions are proposedto obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.
A Method for the Detection of Decrease in Power in PV Systems Using Satellite Data  [PDF]
Kota Kawasaki, Keiichi Okajima
Smart Grid and Renewable Energy (SGRE) , 2019, DOI: 10.4236/sgre.2019.101001
Abstract: In this paper, a method to detect a decrease in the output power of photovoltaic systems is proposed. This method is based on using satellite irradiance data. In addition, fault detection is carried out with only one day’s data in this method. Thus, the time elapses since the decrease in output is shorter than with the other methods. In order to mitigate the error in satellite data and improve the accuracy of fault detection, data extraction is carried out, which consists of two steps. In the first step, effective data are extracted by setting a lower irradiance limit. In the second step, “Calculation day” is determined depending on the number of effective data in one day. Fault detection, which is only conducted on the Calculation day, is conducted by comparing the expected power and the measured power. The parameters used in this study were optimized by testing 45 systems that appear normal. Subsequently, 340 systems were analyzed with the proposed method, using optimized parameters. The results showed the effectiveness of our method from the viewpoints of both accuracy and time required. In addition, three data extraction methods were considered to distinguish between the permanent decrease caused by failure, and the temporary decrease caused by partial shade. Fuzzy cluster analysis showed the best result among the three methods used.
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