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A Novel Reconfigurable Computing Architecture for Image Signal Processing Using Circuit-Switched NoC and Synchronous Dataflow Model  [PDF]
Feitian Li,Fei Qiao,Qi Wei,Huazhong Yang
Computer Science , 2013,
Abstract: In this paper, a novel reconfigurable architecture is proposed for multifunctional image signal processing systems. A circuit-switched NoC is used to provide interconnection because the non-TMD links ensure fixed throughput, which is a desirable behavior for computational intensive image processing algorithms compared with packet-switched NoC. Image processing algorithms are modeled as synchronous dataflow graphs which provide a unified model for general computing procedure. An image processing system is considered as several temporally mutually exclusive algorithms. Thus, their dataflow graph representations could be considered as a group and a merging algorithm could be applied to generate a union graph while eliminating spatial redundancy for area consumption optimization. After the union graph have been mapped and routed on the NoC, the reconfigurable system could be configured to any of its target image processing algorithms by properly setting the NoC topology. Experiments show the demo reconfigurable system with two image processing applications cost 26.4% less hardware resource, compared with the non-reconfigurable implementations.
A Novel Custom Topology Generation for Application Specific Network-on-chip Using Genetic Algorithm Optimization Technique  [PDF]
M. Maheswari
Journal of Artificial Intelligence , 2013,
Abstract: In Networks-on-chips (NoC), the main sources of power consumption are global interconnection links and routers. In Application Specific NoC (ASNoC) power can be minimized by mapping the cores on the application specific topology (custom topology) rather than mapping on the standard topologies. In ASNoC, the design of the topology plays an important role in minimizing the power consumption and hop count. In this study, we propose a novel topology generation algorithm using genetic algorithm optimization technique to generate a custom topology for ASNoC architectures. We applied the proposed algorithm to six benchmark video applications MPEG 4 decoder, VOPD, MWD, mp3 audio encoder, mp3 audio decoder and DSP. The proposed topology generation algorithm achieves significant amount of power saving and decrease in the average number of hop count compared to the existing custom topology generation algorithms.
Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications  [cached]
Linlin Zhang,Virginie Fresse,Mohammed Khalid,Dominique Houzet
EURASIP Journal on Embedded Systems , 2009, DOI: 10.1155/2009/542035
Abstract: The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional Network on Chip (NoC) is not optimal for dataflow applications with large amount of data. On the opposite, point-to-point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data. For data communication inside the architecture, an efficient time-division multiplexed (TDM) architecture is proposed. This NoC uses a Fat Tree (FT) topology with Virtual Channels (VCs) and flit packet-switching with fixed routes. Two versions of the NoC are presented in this paper. The results of their implementations and their Design Space Exploration (DSE) on Altera Stratix II are analyzed and compared with a point-to-point communication and illustrated with a multispectral image application. Results show that a point-to-point communication scheme is not efficient for large amount of multispectral image data communications. An NoC architecture uses only 10% of the memory blocks required for a point-to-point architecture but seven times more logic elements. This resource allocation is more adapted to image analysis algorithms as memory elements are a critical point in embedded architectures. An FT NoC-based communication scheme for data transfers provides a more appropriate solution for resource allocation.
Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications  [cached]
Zhang Linlin,Fresse Virginie,Khalid Mohammed,Houzet Dominique
EURASIP Journal on Embedded Systems , 2009,
Abstract: The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional Network on Chip (NoC) is not optimal for dataflow applications with large amount of data. On the opposite, point-to-point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data. For data communication inside the architecture, an efficient time-division multiplexed (TDM) architecture is proposed. This NoC uses a Fat Tree (FT) topology with Virtual Channels (VCs) and flit packet-switching with fixed routes. Two versions of the NoC are presented in this paper. The results of their implementations and their Design Space Exploration (DSE) on Altera Stratix II are analyzed and compared with a point-to-point communication and illustrated with a multispectral image application. Results show that a point-to-point communication scheme is not efficient for large amount of multispectral image data communications. An NoC architecture uses only 10% of the memory blocks required for a point-to-point architecture but seven times more logic elements. This resource allocation is more adapted to image analysis algorithms as memory elements are a critical point in embedded architectures. An FT NoC-based communication scheme for data transfers provides a more appropriate solution for resource allocation.
Low Power NoC Switch using Novel Adaptive Virtual Channels
Rabab Ezz-Eldin,Magdy A. El-Moursy,Amr M. Refaat
International Journal of Computer Science Issues , 2011,
Abstract: Adaptive Virtual Channel (AVC) is proposed as a novel technique to achieve low power NoC switch. Power supply gating is employed to reduce the power dissipation of NoC switch without degrading network performance. Hierarchical multiplexing tree is used to achieve efficient AVC. AVC could reduce both dynamic and leakage power of the switch. Hierarchical multiplexing tree decreases the area of the switch which reduces the dynamic power by 60%. Using the leakage power reduction technique, the average leakage power consumption of Adaptive Virtual Channels is reduced by up to 97%.
NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology  [cached]
Xingang Ju,Liang Yang
International Journal of Information Technology and Computer Science , 2011,
Abstract: Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, it introduces the basic concept and architecture of the NoC, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding, routing algorithm and node degree routing direction are designed. Thirdly, the programming and simulation of 2×4 NoC interconnection architecture are designed, and it achieves uninterrupted operation. The result shows the correctness of the interconnection architecture design. Finally, it chooses XC4VSX55-12ff1148 of vertext 4 to synthesize, the maximum frequency can up to 268 MHz, which provides foundation of subsequent research and application.
A topology visualisation tool for large-scale communications networks  [PDF]
Yuchun Guo,Changjia Chen,Shi Zhou
Computer Science , 2006,
Abstract: A visualisation tool is presented to facilitate the study on large-scale communications networks. This tool provides a simple and effective way to summarise the topology of a complex network at a coarse level.
A Novel Elliptic curve cryptography Processor using NoC design  [PDF]
Hamid Javashi,Reza Sabbaghi-Nadooshan
International Journal of Computer Science Issues , 2011,
Abstract: In this paper, we propose an elliptic curve key generation processor over GF(2m) and GF(P) with Network-on-Chip (NoC) design scheme based on binary scalar multiplication algorithm. Over the Two last decades, Elliptic Curve Cryptography (ECC) has gained increasing acceptance in the industry and the academic community. This interest is mainly caused by the same level of security with relatively small keys provided by ECC comparing to large key size in Rivest Shamir Adleman (RSA). Parallelism can be utilized in different hierarchy levels as shown in many publications. By using NoC, a new method with the reduced latency of point multiplication (with parallel field arithmetic) is introduced in this paper.
A Novel Elliptic curve cryptography Processor using NoC design  [PDF]
Hamid Javashi,Reza Sabbaghi-Nadooshan
Computer Science , 2011,
Abstract: In this paper, we propose an elliptic curve key generation processor over GF(2m) and GF(P) with Network-on-Chip (NoC) design scheme based on binary scalar multiplication algorithm. Over the Two last decades, Elliptic Curve Cryptography (ECC) has gained increasing acceptance in the industry and the academic community. This interest is mainly caused by the same level of security with relatively small keys provided by ECC comparing to large key size in Rivest Shamir Adleman (RSA). Parallelism can be utilized in different hierarchy levels as shown in many publications. By using NoC, a new method with the reduced latency of point multiplication (with parallel field arithmetic) is introduced in this paper.
Improved Structure for Mesh Topology Based on NoC and its Routing Algorithm
一种对片上网络中Mesh结构的改进策略及路由算法

蒋明,孟铃珊
计算机科学 , 2012,
Abstract: Mesh structure becomes a widely used NoC topology due to its simplicity, regularity, easy to implement and expand. This paper improved the 2D-Mesh structure. VMesh structure which connects every vertex to each other was presented. A deadlock-free routing algorithm based on this structure was proposed too. Finally,we proved that VMesh structure decreases the network diameter and the ideal average communication delay, increases the ideal throughput by detailed calculations. We also emulated the topology and the algorithm with gpNoCsim simulator and our results demonstrated a certain reduction in the average packet delay and routing hops.
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