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A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology  [PDF]
Chih-Yao Huang,Fu-Chien Chiu
Advances in Materials Science and Engineering , 2013, DOI: 10.1155/2013/905686
Abstract: A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case. 1. Introduction Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems. An NMOSFET has been the most popular ESD protection candidate for a long time. Since the shrinking of device size advances continually, the ESD capability of the NMOS device encounters more challenges [1–7]. A gate-grounded NMOS (GGNMOS) can no longer satisfy the ESD protection mission easily. ESD NMOS protection devices usually need the large width size to deal with ESD events. This results in multifinger layout style which is commonly used in practical IC I/O area. But it also has a critical drawback which is not favorable for the ESD protection requirement. The conduction current is usually unevenly distributed along the width direction of the multifingers. Gate-coupling technique using the property that increases the gate bias can reduce the first trigger point of the NMOS device and enable uniform ESD current distribution [4, 8, 9]. Although gate-coupling technique can improve the ESD capability, it still has gate overdriven effect if the gate voltage coupled is much larger than its threshold voltage, and this leads to serious ESD degradation. Furthermore, inserted or butting substrate pickups in the source diffusion region of the ESD NMOS device in deep submicrometer technology also degraded ESD reliability seriously. Such layout style has been strictly prohibited in practical ESD design applications by the technology design rules. Therefore, in this work, a new substrate-and-gate triggering (SGT) structure that utilizes dynamic
Design on an ESD Protection Circuit with GG-NMOS Structure in CMOS Technology
CMOS工艺中GG-NMOS结构ESD保护电路设计

Du Ming,Hao Yue,Zhu Zhiwei,
杜鸣
,郝跃,朱志炜

半导体学报 , 2005,
Abstract: An ESD protection circuit which uses a GG-NMOS structure is presented.The operating principle and test results are depicted.An improved project,gate-couple technology,on the circuit is presented,and the anticipated effect is achieved.The ability of the circuit achieves class 2 of the human-body model.It is also indicated that ESD induces damage of the gate oxide with microcosmic mechanisms,where ESD occurs based on simulation.
A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices  [PDF]
Jin Young Choi
Communications and Network (CN) , 2010, DOI: 10.4236/cn.2010.21002
Abstract: For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.
高中段大面积矿房底柱回收护顶层留设研究  [PDF]
文志杰, 朱永鹏
金属矿山 , 2009,
Abstract: 针对高中段大面积矿房底柱回收时上覆充填体控制要求,建立了进路回采工作面顶板力学状态模型,应用有限差分模拟软件FLAC3D,计算了不同矿柱和进路宽度留设时矿体的稳定性,论证了采用超前注浆上向进路连续回采采矿法回采底柱的可行性,提出了底柱回采前的一系列安全技术措施:超前注浆造顶、打长锚索加强支护、留设护顶层。在此护顶层控制下,上覆充填体的下沉得到了有效控制,使底柱得以安全回收。
西南山区机场高填方边坡反压护道优化设计  [PDF]
陈金锋,宋二祥
工程力学 , 2012, DOI: 10.6052/j.issn.1000-4750.2010.08.0610
Abstract: 针对西南山区机场高填方地基存在有限深度相对软弱土层的工程地质情况,提出单级反压护道的优化设计方法及优化设计中所涉及到的各类典型滑移面稳定安全系数的简化计算方法,并对其进行了证明及验证,分析了所提方法计算结果与强度折减有限元法的差别大小及方法的适用性。验证结果表明:所提方法计算的安全系数与有限元计算结果的相对误差均不超过12%;计算的反压护道断面尺寸相对误差不超过20%;应用于有硬壳层的工程地质条件或有反压护道的典型滑移面时,误差更小。
在软土地基上有反压护道路堤及堤坝的稳定计算  [PDF]
张玉成,杨光华,胡海英,张有详
岩土力学 , 2007,
Abstract: 用反压护道对软土路基进行处理,是保证路堤及堤坝稳定常用的工程措施之一。而目前较常使用的极限平衡法在对有反压护道的路堤及堤坝稳定性进行分析计算时,其结果及搜索到的滑动面位置和形状与实际差别较大。通过强度折减分析了不同工况下有反压护道的路堤的稳定性,并与极限平衡法进行了对比,结果表明,强度折减法的分析结果更接近工程实际情况。利用早期得出的复杂荷载作用下路堤的填土极限高度计算公式,实现用填土极限高度控制路堤的稳定性。最后,以工程实例验证了强度折减和填土极限高度判断有反压护道路堤稳定性是切实可行的。
“三软”倾斜厚煤层综放工作面护巷煤柱尺寸留设研究  [PDF]
李金贵
煤炭工程 , 2014, DOI: 10.11799/ce201408004
Abstract: 论文针对三软厚煤层综放工作面护巷煤柱尺寸展开研究,采用理论分析与数值模拟两种手段。通过理论计算得到文明煤矿开采5#煤层的两综放工作面之间留设煤柱尺寸不小于19.8m,为进一步验证理论计算的客观性,采用计算机数值模拟了15m,20m,25m,30m,35m,40m六种方案,综合煤柱稳定性与支承应力分布,最终确定留设煤柱尺寸为20m至25m之间。最后与现留设40m宽煤柱进行对比,研究结果可提高回采率7.9%,对于类似矿井具有一定的参考价值。
一种填方路堤反压护道断面设计的解析方法研究  [PDF]
赵宁雨,梁波,黄锋,刘毅
岩土力学 , 2015,
Abstract: 针对软弱地基上的高速公路填方路堤稳定性问题,利用整体圆弧法稳定性分析原理,推导了同时考虑滑动面上黏聚力和内摩擦角联合作用的平衡方程;并将滑面上内摩擦角在滑面切向方向上的作用等效为黏聚力作用,提出在此条件下的等效黏聚力概念;进而利用平衡方程和等效黏聚力讨论了合理反压护道宽度和高度的确定方法。以某高速公路反压护道工程为背景,进行了护道断面尺寸的设计计算和分析,并将安全系数和滑体特征与规范推荐方法进行了对比分析。结果表明:相对只考虑黏聚力的计算结果,综合考虑黏聚力和内摩擦角联合作用的分析方法更接近大部分软弱地基内摩擦角非零的工程实际条件,且在获得相同安全系数时具有更优的断面尺寸(节约用地和土方量);该方法与规范推荐方法计算的安全系数有紧密的联系,其值取1.05时与规范容许值较为吻合;该方法能避免设计中依靠经验反复试算确定护道尺寸的盲目性,可减少设计工作量。
反压护道在地方一级公路中的应用  [PDF]
张书生,吴志高
公路交通科技 , 2004,
Abstract: 反映金宜公路钱资荡软基段,变560m特大桥为100m大桥,其余460m采用反压护道处理的办法。根据路堤稳定性验算和沉降量计算结果,确定路基填土的速率,进行施工过程中的沉降观测,同时估算了预抛高厚度和最终沉降量。这种处理方法可降低工程造价1500余万元,取得较好的经济效益,阐明在地方一级公路施工中可采用时间换金钱软基处理的方法。
Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13- m silicide CMOS technology
0.13微米硅化物 CMOS工艺下版图参数对栅极接地 NMOS晶体管骤回特性的影响

Jiang Yuxi,Li Jiao,Ran Feng,Cao Jialin,Yang Dianxiong,
姜玉稀
,李娇,冉峰,曹家麟,杨殿雄

半导体学报 , 2009,
Abstract: 本文中,在 0.13微米硅化物 CMOS工艺下, 设计了不同版图尺寸和不同版图布局的栅极接地 NMOS器件。TLP测量技术用来获得器件的骤回特性。 文章分析了器件版图参数和器件骤回特性之间的关系。TCAD器件仿真软件被用来解释证明这些结论.通过这些结论,电路设计者可以预估栅极接地NMOS器件在ESD大电流情况下的特性,由此在有限的版图面积下设计符合 ESD保护要求的栅极接地 NMOS器件。本文同时给出了优化后的 0.13微米硅化物工艺下 ESD版图规则。
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