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A novel high performance ESD power clamp circuit with a small area
A Novel High Performance ESD Power Clamp Circuit with Small Area

Yang Zhaonian,Liu Hongxi,Li Li,Zhuo Qingqing,

半导体学报 , 2012,
Abstract: A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.
A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

Pan Hongwei,Liu Siyang,Sun Weifeng,
Pan Hongwei
,Liu Siyang,Sun Weifeng

半导体学报 , 2013,
Abstract: The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to eliminate latch-up risk, this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current. The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.79199
Abstract: In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDDbus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.
A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices  [PDF]
Jin Young Choi
Communications and Network (CN) , 2010, DOI: 10.4236/cn.2010.21002
Abstract: For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.
Investigation of the polysilicon p--i--n diode and diode string as a process compatible and portable ESD protection device

Jiang Yibo,Du Huan,Han Zhengsheng,

半导体学报 , 2012,
Abstract: The polysilicon p-i-n diode displayed noticeable process-compatibility and portability in advance technologies as ESD protection device. The paper presented reverse breakdown, current leakage and capacitance characteristics for the fabricated polysilicon p-i-n diode. To evaluate ESD robustness forward and reverse TLP I-V characteristics were measured also. Besides polysilicon p-i-n diode string was investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. To explain the effects of device parameter, analysis and discussion about the inherent properties of polysilicon p-i-n diode were processed finally.
Two step current increases in glow discharge development in neon filled diode at 4 mbar  [PDF]
Radovi? Miodrag K.,Maluckov ?edomir A.,Miti? Slobodan D.,Radovanovi? Bratislav
Facta Universitatis Series : Physics, Chemistry and Technology , 2007, DOI: 10.2298/fupct0701001r
Abstract: The results are presented of investigating temporal and spatial development of electrical glow discharge in a neon filled tube under 4mbar pressure. Linear increasing voltage (at 5 V/s increasing voltage rate) is applied to the gas diode. Time dependence of 585.2 nm line light emitted from negative glow is observed from various positions in the diode during formation of electrical discharge. The results show that the development of glow discharge starts in the gap, and propagates to the cathode and in the space around and behind the cathode. An unexpected two-step current rise is found. In the stationary regime, most of the emitted light occupied the cathode carrier rod. This indicates the position where the secondary electron emission is intensive. It corresponds to the second step in the current increase app. 3 ms after the breakdown has already taken place. It is assumed that this step originates from different surface characteristics of the rode material. The analysis of time dependencies of the current and light from the negative glow, from different positions in the gas diode, suggests that the observation of deexcitation processes in gas can be used for determination of early discharge formative processes, as well as processes that lead to the stationary regime in the gas diode tube.
Analysis On Electrostatic Discharge Protection of Electronics Dictionary  [cached]
Qiang DU,Guo-jian TIAN,Hao WANG
Advances in Natural Science , 2008, DOI: 10.3968/41
Abstract: The ESD protection for an electronic dictionary was studied, and detailed countermeasures are presented. By the presented steps against the ESD, the electronic dictionary can satisfy the requirement of 4 kV ESD in the mode of contact discharge, 8 kV ESD in the mode of air discharge. Key words: electrostatic discharge; electronic dictionary; protection; filter; electrostatic interference
Frequency Stabilization of a 369 nm Diode Laser by Nonlinear Spectroscopy of Ytterbium Ions in a Discharge  [PDF]
Michael W Lee,Marie Claire Jarratt,Christian Marciniak,Michael J Biercuk
Physics , 2014, DOI: 10.1364/OE.22.007210
Abstract: We demonstrate stabilisation of an ultraviolet diode laser via Doppler free spectroscopy of Ytterbium ions in a discharge. Our technique employs polarization spectroscopy, which produces a natural dispersive lineshape whose zero-crossing is largely immune to environmental drifts, making this signal an ideal absolute frequency reference for Yb$^+$ ion trapping experiments. We stabilise an external-cavity diode laser near 369 nm for cooling Yb$^+$ ions, using amplitude-modulated polarisation spectroscopy and a commercial PID feedback system. We achieve stable, low-drift locking with a standard deviation of measured laser frequency ~400 kHz over 10 minutes, limited by the instantaneous linewidth of the diode laser. These results and the simplicity of our optical setup makes our approach attractive for stabilization of laser sources in atomic-physics applications.
ESD Transient Model of Vertical DMOS Power Devices

Li Zehong,Zhou Chunhu,Hu Yonggui,Liu Yong,Zhang Bo,Xu Shiliu,

半导体学报 , 2008,
Abstract: Based on the equivalent circuit of VDMOS,the initial condition and transient response process are analyzed and the ESD transient model of the power VDMOS device is obtained.Results show that the ESD transient discharge process is correctly depicted with this model,which resolves the problem of the insufficient initial conditions of other models.Based on this model,the relationships between ESD threshold voltage and gate input protection series resistance,breakdown voltage,and parasitic dynamic resistance of the Zener diodes,and gate-source capacitance and gate oxide thickness of the power VDMOS,are obtained.This model can guide the design of ESD protection for power VDMOSs
Emerging Challenges in ESD Protection for RF ICs in CMOS

Wang Albert,Lin Lin,Wang Xin,Liu Hainan,Zhou Yumei,

半导体学报 , 2008,
Abstract: On-chip electrostatic discharge (ESD) protection design has become an emerging challenge for radio-frequency (RF) integrated circuits (IC) design as IC technologies migrate into the very-deep-sub-micron (VDSM) regime and RF ICs move into multi-GHz operations.The key problem originates from the complex interaction between the ESD protection circuitry and the core RF IC circuit under protection.This paper discusses the recent development in RF ESD protection research and design,outlining emerging challenges,new design methods,and novel RF ESD protection solutions.
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