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Design Of Cache Memory With Cache Controller Using VHDL
International Journal of Innovative Research in Science, Engineering and Technology , 2013,
Abstract: We Report On The Design Of Efficient Cache Controller Suitable For Use In FPGA-Based Processors. Semiconductor Memory Which Can Operate At Speeds Comparable With The Operation Of The Processor Exists; It Is Not Economical To Provide All The Main Memory With Very High Speed Semiconductor Memory. The Problem Can Be Alleviated By Introducing A Small Block Of High Speed Memory Called A Cache Between The Main Memory And The Processor. Set-Associative Mapping Compromise Between A Fully Associative Cache And A Direct Mapped Cache, As It Increases Speed. With Reference To Set Associative Cache Memory We Have Designed Cache Controller. Spatial Locality Of Reference Is Used For Tracking Cache Miss Induced In Cache Memory. In Order To Increase Speed , Less Power Consumption And Tracking Of Cache Miss In 4-Way Set Associative Cache Memory, FPGA Cache Controller Will Proposed By This Research Work . We Believe That Our Design Work Achieves Less Circuit Complexity, Less Power Consumption And High Speed In Terms Of FPGA Resource Usage
Implementation of AXI Design core with DDR3 memory controller for SoC  [PDF]
Darshana Dongre,,Prof.Anil Kumar Sahu
International Journal of Computer Technology and Electronics Engineering , 2011,
Abstract: This paper discusses the overall architecture of AMBA AXI design core along with its advantage with DDR3 memory controller and operation of its individual sub blocks. It takes care of the DDR3 initialization and various timing requirements of the DDR3 memory. The memory controller works as an intelligent bridge between the AXI host and DDR3 memory. Our design has been implemented with respect to latency reduction and improvement in various performance parameters and the design is simulated on Modelsim and synthesized on Xilinx successfully.
The Space of Remembering: Collective Memory and the Reconfiguration of Contested Space in Argentina’s ESMA  [PDF]
Parsons, Emily
452o F : Revista de Teoría de la Literatura y Literatura Comparada , 2011,
Abstract: This paper explores the ongoing history of the ESMA museum’s developmentand argues that the intrinsic and conflictual collective memory work involved is characterized by competing desires to remember and to forget, rooted in the physical,visible, and public space of ESMA.
Testing of AMBA Compliant Memory Controller using Pattern Generator/ Logic Analyser  [PDF]
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering , 2013,
Abstract: With the growing imbalance between processor and memory performance it becomes more and more important to optimize the memory controller features to obtain the maximum possible performance out of the memory subsystem. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. Improvements in memory latency and bandwidth have not kept pace with reductions in execution time of the instruction. Caches have been used extensively to compensate this mismatch, but some applications do not use caches effectively. As a result, the memory access time has been a hurdle which limits the performance of the system. The problem can be handled by designing a Memory Controller. This paper revolves around implementing and testing the Advanced Microcontroller Bus Architecture (AMBA) compliant Memory Controller as an Advanced High-performance Bus (AHB) slave. The whole design is captured using Verilog, configured to a FPGA target device belonging to the Spartan 3A and Spartan 3AN family using Xilinx compiler, and simulated with ModelSim. The resulting bit file after compiling is then downloaded to a TKB3S board. The FPGA board is connected to the ADM’s LG320/LGLITE Integrated Logic Analyser and Pattern Generator for testing and verifying the design.
High Speed FSM-based programmable Memory Built-In Self-Test (MBIST) Controller  [PDF]
Dr. K Padma Priya
International Journal of Computer Science and Mobile Computing , 2013,
Abstract: This paper proposed a High speed FSM-based controller for programmable memory built-in self test for testing memory devices. This technique is popular because of its flexibility of new test algorithms. The architecture of controller is designed to implement a new test algorithm has less number of operations and this algorithm emphasis testing of high density memory ICs either faulty or good .The components of controller is studied and designed using Verilog HDL. The analysis of the timing, logic area usage and speed are presented.
Multiport Analysis by Padé Approximation
Goker Sener
PIER , 2012, DOI: 10.2528/PIER12011805
Abstract: In this paper, a new method to analyze arbitrary shaped microstrip patch antennas is introduced. This method uses the multiport network model (MNM) together with a mathematical approximation called the "Pade approximation" such that the antenna input impedance obtained from the multiport analysis is approximated as a rational function of polynomials. Then, the roots of the denominator of this rational function are used to determine the antenna resonant characteristics. This new method is more time efficient than the standard multiport analysis because the evaluations are made at a single frequency. In the standard method, evaluations are made at multiple frequency values throughout the analysis. Results obtained by the new method are verified using the examples of rectangular and slot loaded compact microstrip patch antennas. Computational efforts for both procedures are presented.
Multiport Impedance Quantization  [PDF]
Firat Solgun,David P. DiVincenzo
Physics , 2015,
Abstract: With the increase of complexity and coherence of superconducting systems made using the principles of circuit quantum electrodynamics, more accurate methods are needed for the characterization, analysis and optimization of these quantum processors. Here we introduce a new method of modelling that can be applied to superconducting structures involving multiple Josephson junctions, high-Q superconducting cavities, external ports, and voltage sources. Our technique, an extension of our previous work on single-port structures [1], permits the derivation of system Hamiltonians that are capable of representing every feature of the physical system over a wide frequency band and the computation of T1 times for qubits. We begin with a black box model of the linear and passive part of the system. Its response is given by its multiport impedance function Zsim(w), which can be obtained using a finite-element electormagnetics simulator. The ports of this black box are defined by the terminal pairs of Josephson junctions, voltage sources, and 50 Ohm connectors to high-frequency lines. We fit Zsim(w) to a positive-real (PR) multiport impedance matrix Z(s), a function of the complex Laplace variable s. We then use state-space techniques to synthesize a finite electric circuit admitting exactly the same impedance Z(s) across its ports; the PR property ensures the existence of this finite physical circuit. We compare the performance of state-space algorithms to classical frequency domain methods, justifying their superiority in numerical stability. The Hamiltonian of the multiport model circuit is obtained by using existing lumped element circuit quantization formalisms [2, 3]. Due to the presence of ideal transformers in the model circuit, these quantization methods must be extended, requiring the introduction of an extension of the Kirchhoff voltage and current laws.
Scheme for implementing atomic multiport devices  [PDF]
Jessica J. Cooper,David W. Hallwood,Jacob A. Dunningham
Physics , 2007,
Abstract: Multiport generalizations of beam splitters are the key component in multipath interferometers, which are important in a range of quantum state engineering and precision measurement schemes. Here we propose a straightforward method for implementing multiport devices for atoms trapped in optical ring lattices. These devices are interesting as atoms have certain properties (such as mass) that photons do not and the ring configuration makes them useful for applications such as precision gyroscopes. We discuss how they could be employed in useful measurement schemes and investigate how practical considerations limit the size of the devices that can be achieved by this method.
Design of Low Power Double Data Rate 3 Memory Controller with AXI compliant
Vijaykumar,R K Karunavathi,Vijay Prakash
International Journal of Engineering and Advanced Technology , 2012,
Abstract: As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. The next generation family of Double Data Rate (DDR)RAMs are DDR3 RAM. DDR3 RAMs offer numerous advantages compared to DDR2. These devices are lower power, they operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. DDR3 memory devices provide a 30% reduction in power consumption compared to DDR2, primarily due to smaller die sizes and the lower supply voltage (1.5V for DDR3 vs. 1.8V for DDR2). This paper represents the overall design and architecture of Low power Double Data rate 3(DDR3) memory controller. In this paper clock gating is used as a low power technique .
Zero-Transmission Law for Multiport Beam Splitters  [PDF]
Malte Christopher Tichy,Markus Tiersch,Fernando de Melo,Florian Mintert,Andreas Buchleitner
Physics , 2010, DOI: 10.1103/PhysRevLett.104.220405
Abstract: The Hong-Ou-Mandel effect is generalized to a configuration of n bosons prepared in the n input ports of a Bell multiport beam splitter. We derive a strict suppression law for most possible output events, consistent with a generic bosonic behavior after suitable coarse graining.
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