Abstract:
Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology.

Abstract:
Based on visual model,integer DCT(Discrete Cosine Transform) and Hash functions,an novel watermarking technique is proposed.Complexity is reduced and image quality is improved compare with the existed DCT methods due to the introduction of integer DCT.Moreover,visual model results in raise of resistant for JPEG compression and other image processing.New watermarking technique is high security.

Abstract:
A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α？ = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α？ = 4.5958 for an 8% reduction in total power ( PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy.

Abstract:
An algebraic integer (AI) based time-multiplexed row-parallel architecture and two final-reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8$\times$8 2-D DCT which is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on (i) optimized Dempster-Macleod multipliers and (ii) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on FPGA chip. Six designs, for 4- and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented and measured. The maximum clock rate and block-rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8$\times$307.787$\approx$2.462 GHz if eventually embedded in a real-time video-processing system. The equivalent frame rate is about 1187.35 Hz for the image size of 1920$\times$1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.

Abstract:
A new class of matrices based on a parametrization of the Feig-Winograd factorization of 8-point DCT is proposed. Such parametrization induces a matrix subspace, which unifies a number of existing methods for DCT approximation. By solving a comprehensive multicriteria optimization problem, we identified several new DCT approximations. Obtained solutions were sought to possess the following properties: (i) low multiplierless computational complexity, (ii) orthogonality or near orthogonality, (iii) low complexity invertibility, and (iv) close proximity and performance to the exact DCT. Proposed approximations were submitted to assessment in terms of proximity to the DCT, coding performance, and suitability for image compression. Considering Pareto efficiency, particular new proposed approximations could outperform various existing methods archived in literature.

Abstract:
A polynomial transform-based fast algorithm for integer 2D Discrete Cosine Transform(2D-DCT) was proposed.The 2D-DCT was transformed to some 1D-DCT and summing calculation by polynomial transform,so the computational complexity was reduced.The integer DCT was implemented by lifting matrix to promote efficiency,and the transformed signal could be reconstructed completely.

Abstract:
Robustness and invisibility are used to evaluate the performance of the watermark algorithm.In order to design a complicated scheme with both preferable robustness and invisibility with low complexity,in this paper,a new watermarking based on Integer DCT scheme is proposed.At first we studied the integral transform characteristic of the frequency coefficients,to find out the coefficients which are fit to be embedded and the relation of theirs embedded threshold.Then we formed a new image by extract each block DC coefficient,and select out numbers of the blocks with complex texture.At last,by Integer DCT,the digital watermark signals were embedded into the frequency coefficients of the theses blocks.Experimental results show that the proposed watermarking scheme ensures that the invisibility of watermark,and have good robustness against various attacks such as JPEG compression,noise,filter and so on,even if under the mosaic attack.

Abstract:
In this paper the authors present a novel integer reversible DCT based embedded image coding scheme, which can integrate lossy and lossless coding schemes perfectly. Image coding is of great interest in applications where efficiency with respect to data storage or transmission bandwidth is sought. The discrete cosine transform(DCT) has been applied extensively to the area of image coding. It has nice decorrelation and excellent energy compaction properties and it can be easily implemented by hardware. In this paper the integer DCT transform is implemented by factoring the float DCT transform matrix into integer reversible transform series. Then the authors apply the series of matrices to image samples, and encode the coefficients by several effective coding algorithms. The simulation results illustrate that the integer DCT coding scheme is superior to the float DCT coding method in lossless coding, and the coding performance of integer DCT is close to that of float DCT in lossy coding.

Abstract:
In this article we establish an exponential lower bound on the Graver complexity of integer programs. This provides new type of evidence supporting the presumable intractability of integer programming. Specifically, we show that the Graver complexity of the incidence matrix of the complete bipartite graph $K_{3,m}$ satisfies $g(m)=\Omega(2^m)$, with $g(m)\geq 17\cdot 2^{m-3}-7$ for every $m>3$ .