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A Flip-Chip AlGaInP LED with GaN/Sapphire Transparent Substrate Fabricated by Direct Wafer Bonding
LIANG Ting,GUO Xia,GUAN Bao-Lu,GUO Jing,GU Xiao-Ling,LIN Qiao-Ming,SHEN Guang-Di,

中国物理快报 , 2007,
Abstract: A red-light AlGaInP light emitting diode (LED) is fabricated by using direct wafer bonding technology. Taking N-GaN wafer as the transparent substrate, the red-light LED is flip-chiped onto a structured silicon submount. Electronic luminance (EL) test reveals that the luminance flux is 130% higher than that of the conventional LED made from the same LED wafer. Current--voltage (I--V) measurement indicates that the bonding processes do not impact the electrical property of AlGaInP LED in the small voltage region (V<1.5V). In the large voltage region (V>1.5V), the I--V characteristic exhibits space-charge-limited currents characteristic due to the p-GaAs/n-GaN bonding interface.
III-V/Si Wafer Bonding Using Transparent, Conductive Oxide Interlayers  [PDF]
Adele C. Tamboli,Maikel F. A. M. van Hest,Myles A. Steiner,Stephanie Essig,Emmett E. Perl,Andrew G. Norman,Nick Bosco,Paul Stradins
Physics , 2015,
Abstract: We present a method for low temperature plasma-activated direct wafer bonding of III-V materials to Si using a transparent, conductive indium zinc oxide interlayer. The transparent, conductive oxide (TCO) layer provides excellent optical transmission as well as electrical conduction, suggesting suitability for Si/III-V hybrid devices including Si-based tandem solar cells. For bonding temperatures ranging from 100$^{\circ}$C to 350$^{\circ}$C, Ohmic behavior is observed in the sample stacks, with specific contact resistivity below 1 $\Omega$cm$^2$ for samples bonded at 200$^{\circ}$C. Optical absorption measurements show minimal parasitic light absorption, which is limited by the III-V interlayers necessary for Ohmic contact formation to TCOs. These results are promising for Ga$_{0.5}$In$_{0.5}$P/Si tandem solar cells operating at one sun or low concentration conditions.
Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems  [PDF]
J. Iannacci,Jason Tian,S. Sinaga,R. Gaddi,A. Gnudi,M. Bartek
Computer Science , 2007,
Abstract: In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The RF-MEMS package concept used is based on a wafer-level bonding of a capping silicon substrate to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finite-element electromagnetic simulations (Ansoft HFSS). Test structures for electrical characterization have been designed and after their fabrication, measurement results will be compared with simulations.
Effect of Wafer Surface Morphology Characteristics on Wafer Bonding

Chen Bin,Huang Yongqing,REN Xiaomin,

半导体学报 , 2005,
Abstract: A general wafer bonding criterion is deduced from minimum energy principle,which is developed by linear elastic thin plate theory.Under the same framework the effect of macro-scale wafer bow and micro-scale wafer waviness on wafer bonding process are modeled through the elastic strain energy accumulation rate which is the quantity that controls bonding.Model results are discussed respectively in detail.
Comparison of the copper and gold wire bonding processes for LED packaging

Chen Zhaohui,Liu Yong,Liu Sheng,

半导体学报 , 2011,
Abstract: Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.
Wafer bonding solution to epitaxial graphene - silicon integration  [PDF]
Rui Dong,Zelei Guo,James Palmer,Yike Hu,Ming Ruan,John Hankinson,Jan Kunc,Swapan K Bhattacharya,Claire Berger,Walt A. de Heer
Physics , 2013, DOI: 10.1088/0022-3727/47/9/094001
Abstract: The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.
Wafer Direct Bonding Based on UV Exposure

Ma Canghai,Liao Guanglan,Shi Tielin,Tang Zirong,Liu Shiyuan,Nie Lei,Lin Xiaohui,

半导体学报 , 2008,
Abstract: Wafer direct bonding technology has extensive application and broad prospects.UV activation combined with wet chemical cleaning in wafer direct bonding is investigated.An IR detection system,single tensile machine,and FSEM are employed to evaluate the bonding quality.The constant temperature and humility experiment,and the high and low temperature cycle experiment are also performed.It has been demonstrated that this approach can realize wafer direct bonding and enhance the bonding strength.A higher strength can be obtained by controlling the UV exposure time.The bonded wafer treated by constant temperature and humility and high and low temperature cycle can retain a higher bonding strength.Therefore,the process is effective for the wafer direct bonding and has great potential for application.
Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer  [PDF]
Azrul Azlan Hamzah,Jumril Yunas,Burhanuddin Yeop Majlis,Ibrahim Ahmad
Sensors , 2008, DOI: 10.3390/s8117438
Abstract: This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG) as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP) as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.
Anodic bonding using a hybrid electrode with a two-step bonding process

Luo Wei,Xie Jing,Zhang Yang,Li Chaobo,Xia Yang,

半导体学报 , 2012,
Abstract: A two-step bonding process using a novel hybrid electrode is presented. The effects of different electrodes on bonding time, bond strength and the bonded interface are analyzed. The anodic bonding is studied using a domestic bonding system, which carries out a detailed analysis of the integrity of the bonded interface and the bond strength measurement. With the aid of the hybrid electrode, a bubble-free anodic bonding process could be accomplished within 15-20 min, with a shear strength in excess of 10 MPa. These results show that the proposed method has a high degree of application value, including in most wafer-level MEMS packaging.
Strain Field in GaAs/GaN Wafer-Bonding Interface and Its Microstructure
WU Di,GUO Xia,GU Xiao-Ling,LI Yi-Bo,SHEN Guang-Di,

中国物理快报 , 2007,
Abstract: The strain fields in a wafer-bonded GaAs/GaN structure are measured by electron backscatter diffraction (EBSD). Image quality (IQ) of EBSD Kikuchi patterns and rotation angles of crystal lattices as strain sensitive parameters are employed to characterize the distortion and the rotation of crystal lattices in the GaAs--interface--GaN structure, as well as to display the strain fields. The results indicate that the influence region of the strains in the wafer-bonded GaAs/GaN structure is mainly located in GaAs side because the strength of GaAs is weaker than that of GaN. The cross-sectional image of transmission electron microscopy (TEM) further reveals the distortion and the rotation of crystal lattices induced by strains systematically.
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