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DSP implementation of H.264 high performance video encoder
H.264高性能视频编码器的DSP实现

LU Bao-sheng,CHEN Qi-mei,
鹿宝生
,陈启美

计算机应用 , 2005,
Abstract: The design and implementation of H. 264 hign performance video encoder based on TMS320DM642 DSP platform was described. The design of the hardware was introduced firstly, including the choice of DM642 DSP. Then, the eneoder program was ported, and some algorithms focused on sample interpolation and motion estimation were optimized based on the custom operations of DM642. Experiment results show that the real-time H. 264 eneoder can be realized on DM642 by using proposed algorithms, while the high compression efficiency and image quality are preserved.
FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264/AVC  [cached]
Ndili Obianuju,Ogunfunmi Tokunbo
EURASIP Journal on Embedded Systems , 2009,
Abstract: There is an increasing need for high quality video on low power, portable devices. Possible target applications range from entertainment and personal communications to security and health care. While H.264/AVC answers the need for high quality video at lower bit rates, it is significantly more complex than previous coding standards and thus results in greater power consumption in practical implementations. In particular, motion estimation (ME), in H.264/AVC consumes the largest power in an H.264/AVC encoder. It is therefore critical to speed-up integer ME in H.264/AVC via fast motion estimation (FME) algorithms and hardware acceleration. In this paper, we present our hardware oriented modifications to a hybrid FME algorithm, our architecture based on the modified algorithm, and our implementation and prototype on a PowerPC-based Field Programmable System on Chip (FPSoC). Our results show that the modified hybrid FME algorithm on average, outperforms previous state-of-the-art FME algorithms, while its losses when compared with FSME, in terms of PSNR performance and computation time, are insignificant. We show that although our implementation platform is FPGA-based, our implementation results compare favourably with previous architectures implemented on ASICs. Finally we also show an improvement over some existing architectures implemented on FPGAs.
FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264/AVC  [cached]
Obianuju Ndili,Tokunbo Ogunfunmi
EURASIP Journal on Embedded Systems , 2009, DOI: 10.1155/2009/893897
Abstract: There is an increasing need for high quality video on low power, portable devices. Possible target applications range from entertainment and personal communications to security and health care. While H.264/AVC answers the need for high quality video at lower bit rates, it is significantly more complex than previous coding standards and thus results in greater power consumption in practical implementations. In particular, motion estimation (ME), in H.264/AVC consumes the largest power in an H.264/AVC encoder. It is therefore critical to speed-up integer ME in H.264/AVC via fast motion estimation (FME) algorithms and hardware acceleration. In this paper, we present our hardware oriented modifications to a hybrid FME algorithm, our architecture based on the modified algorithm, and our implementation and prototype on a PowerPC-based Field Programmable System on Chip (FPSoC). Our results show that the modified hybrid FME algorithm on average, outperforms previous state-of-the-art FME algorithms, while its losses when compared with FSME, in terms of PSNR performance and computation time, are insignificant. We show that although our implementation platform is FPGA-based, our implementation results compare favourably with previous architectures implemented on ASICs. Finally we also show an improvement over some existing architectures implemented on FPGAs.
Parallel Design and Implementation of Block Mode Selection in Motion Estimation of H.264
H.264运动估计中块模式选择的并行设计

LIAO Yong-hong,
廖永红

计算机科学 , 2008,
Abstract: To facilitate H.264/AVC implement in the application system with high low rate,its coding algorithm needs to be optimized.This paper first analyzes the H.264/AVC encoder deeply,then on the basis of it presents the parallel design program of block mode selection and parallel designs and implements this program.Finally the design program is tested on multi-core server and the testing results show that the encoding speed of the three-step search algorithm after parallel improves by an average of 2.73 times wit...
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos  [PDF]
Marcel M. Corrêa,Mateus T. Schoenknecht,Robson S. Dornelles,Luciano V. Agostini
International Journal of Reconfigurable Computing , 2011, DOI: 10.1155/2011/254730
Abstract: This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV ( ) in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works. 1. Introduction Video coding is an important research area due to the increasing demand for high-definition digital video for applications like video streaming over the internet, digital television broadcasting, video storage, and many others. There are many video coding standards. These standards primarily define two things: a coded representation (or syntax) which describes the visual data in a compressed form and a method to decode the syntax to reconstruct the visual information [1]. The most recent standard is the H.264/AVC (Advanced Video Coding), designed to achieve the highest compression rates when compared to older standards [2]. However, this new standard has a very high computational complexity, which makes it difficult for software implementations to encode high-definition videos in real time when using the H.264/AVC complex features. For this reason, dedicated hardware architectures are a good solution for fast and efficient high-definition video coding. A hardware implementation is also required when the video encoder or decoder is inserted in an embedded system like a cell phone or a digital camera, and in this case, a high-throughput and low-power solution is essential. A raw digital video has a high amount of redundant information that can be explored for compression purposes. There are three kinds of redundancy: the spatial redundancy is the similarity in homogeneous areas within a frame, the temporal redundancy is the similarity between sequential frames, and finally, the entropic redundancy is the similarity in the bit stream representation [1]. Figure 1 presents a block diagram of the H.264/AVC encoder, with its main operations: Inter-Frames Prediction, composed by the Motion Estimation (ME) and the Motion Compensation (MC) modules, Intra-Frame Prediction, Forward Transforms (T) and Quantization (Q), Entropy Coding, Inverse Quantization (IQ) and Transformations (IT), and Deblocking Filter [2].
Content Adaptive True Motion Estimator for H.264 Video Compression
J. Huska,P. Kulla
Radioengineering , 2007,
Abstract: Content adaptive true motion estimator for H.264 video coding is a fast block-based matching estimator with implemented multi-stage approach to estimate motion fields between two image frames. It considers the theory of 3D scene objects projection into 2D image plane for selection of motion vector candidates from the higher stages. The stages of the algorithm and its hierarchy are defined upon motion estimation reliability measurement (image blocks including two different directions of spatial gradient, blocks with one dominant spatial gradient and blocks including minimal spatial gradient). Parameters of the image classification into stages are set adaptively upon image structure. Due to search strategy are the estimated motion fields more corresponding to a true motion in an image sequence as in the case of conventional motion estimation algorithms that use fixed sets of motion vector candidates from tight neighborhood.
DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation  [PDF]
Gustavo Sanchez,Felipe Sampaio,Marcelo Porto,Sergio Bampi,Luciano Agostini
International Journal of Reconfigurable Computing , 2012, DOI: 10.1155/2012/186057
Abstract: This paper presents a new fast motion estimation (ME) algorithm targeting high resolution digital videos and its efficient hardware architecture design. The new Dynamic Multipoint Diamond Search (DMPDS) algorithm is a fast algorithm which increases the ME quality when compared with other fast ME algorithms. The DMPDS achieves a better digital video quality reducing the occurrence of local minima falls, especially in high definition videos. The quality results show that the DMPDS is able to reach an average PSNR gain of 1.85?dB when compared with the well-known Diamond Search (DS) algorithm. When compared to the optimum results generated by the Full Search (FS) algorithm the DMPDS shows a lose of only 1.03?dB in the PSNR. On the other hand, the DMPDS reached a complexity reduction higher than 45 times when compared to FS. The quality gains related to DS caused an expected increase in the DMPDS complexity which uses 6.4-times more calculations than DS. The DMPDS architecture was designed focused on high performance and low cost, targeting to process Quad Full High Definition (QFHD) videos in real time (30 frames per second). The architecture was described in VHDL and synthesized to Altera Stratix 4 and Xilinx Virtex 5 FPGAs. The synthesis results show that the architecture is able to achieve processing rates higher than 53 QFHD fps, reaching the real-time requirements. The DMPDS architecture achieved the highest processing rate when compared to related works in the literature. This high processing rate was obtained designing an architecture with a high operation frequency and low numbers of cycles necessary to process each block. 1. Introduction Nowadays digital video compression is really a relevant issue. It happens due to the growing development of applications that handle high definition videos, as smart phones, digital cameras, tablets, and so on. These applications would not be possible without video compression. The video bitstream must be drastically reduced to enable the transmission and storage, especially when high definition videos must be processed in real-time. In a digital video there is a lot of redundant information, and this redundancy is explored in the current video coder standards. Neighbor blocks in a frame usually have very similar pixel colors and intensity and the intraframe prediction of the current video coders explore this type of redundancy. The transforms and quantization also contribute to reduce the intraframe redundancy, but in this case, in the frequency domain. In a set of neighbor frames, the information is also very
Fast Motion Estimation and Intermode Selection for H.264  [cached]
Choi Byeong-Doo,Nam Ju-Hun,Hwang Min-Cheol,Ko Sung-Jea
EURASIP Journal on Advances in Signal Processing , 2006,
Abstract: H.264/AVC provides various useful features such as improved coding efficiency and error robustness. These features enable mobile devices to adopt H.264 standard to achieve effective video communications. However, the encoder complexity is greatly increased mainly due to motion estimation (ME) and mode decision. In this paper, we propose a new scheme to jointly optimize intermode selection and ME using the multiresolution analysis. Experimental results show that the proposed method is over 3 times faster than other existing methods while maintaining the coding efficiency.
Rapid algorithm of multi-block motion estimation for H.264
一种用于H.264的快速多块类型运动估计算法

YAN Hong-kui,SHEN Yan-fei,ZHU Zhen-min,XIAO Jian-hua,
颜洪奎
,沈燕飞,朱珍民,肖建华

计算机应用 , 2008,
Abstract: The full search algorithm of H.264 multi-block motion estimation is highly time-consuming. The paper proposed a new multi-block algorithm by speculating motion estimation based on the characteristic of the image's spatial frequency. The results of the experiments show that our algorithm evidently reduces the complexity of motion estimation computing under the condition of keeping good image quality and high bit rate.
An Improved Cross Diamond Motion Search Algorithm Based on H.264  [cached]
Xi Su,Peng Bai,Yuanyuan Wu,Yanping Feng
Journal of Computers , 2011, DOI: 10.4304/jcp.6.12.2603-2606
Abstract: On the price of complexity, the new video compression standard H.264 is more effective than MPEG-4 in compression. Aimed at the motion estimation problem in search rate, a directional search pattern and an improved cross diamond search algorithm which adopts many technologies including prediction of initial search point, suitable search pattern choosing and auxiliary search points are proposed in this paper. Simulation results demonstrate that the improved cross diamond algorithm can effectively enhance search rate under similar PSNR.
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