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Detection of a large valley-orbit splitting in silicon with two-donor spectroscopy  [PDF]
Benoit Roche,Eva Dupont-Ferrier,Benoit Voisin,Manuel Cobian,Xavier Jehl,Romain Wacquez,Maud Vinet,Yann-Michel Niquet,Marc Sanquer
Physics , 2012, DOI: 10.1103/PhysRevLett.108.206812
Abstract: We measure a large valley-orbit splitting for shallow isolated phosphorus donors in a silicon gated nanowire. This splitting is close to the bulk value and well above previous reports in silicon nanostructures. It was determined using a double dopant transport spectroscopy which eliminates artifacts induced by the environment. Quantitative simulations taking into account the position of the donors with respect to the Si/SiO$_2$ interface and electric field in the wire show that the values found are consistent with the device geometry.
Balanced ternary addition using a gated silicon nanowire  [PDF]
J. A. Mol,J. van der Heijden,J. Verduijn,M. Klein,F. Remacle,S. Rogge
Physics , 2011, DOI: 10.1063/1.3669536
Abstract: We demonstrate the proof of principle for a ternary adder using silicon metal-on-insulator single electron transistors (SET). Gate dependent rectifying behavior of a single electron transistor results in a robust three-valued output as a function of the potential of the SET island. Mapping logical, ternary inputs to the three gates controlling the potential of the SET island allows us to perform complex, inherently ternary operations, on a single transistor.
Simulations of gated Si nanowires and 3-nm junctionless transistors  [PDF]
Lida Ansari,Baruch Feldman,Giorgos Fagas,Jean-Pierre Colinge,James C. Greer
Physics , 2010, DOI: 10.1063/1.3478012
Abstract: Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ~1 nm wire diameter and ~3 nm gate length, and that the junctionless transistor may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.
Metal-Gated Junctionless Nanowire Transistors  [PDF]
Mostafizur Rahman,Pritish Narayanan,Csaba Andras Moritz
Computer Science , 2014,
Abstract: Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to conventional CMOS FETs. Previous theoretical and experimental works [1][2] on JNFETs have considered polysilicon gates and silicon-dioxide dielectric. However, with further scaling, JNFETs will suffer from deleterious effects of doped polysilicon such as high resistance, additional capacitance due to gate-oxide interface depletion, and incompatibility with high-k dielectrics[3][4]. In this paper, novel metal- gated high-k JNFETs are investigated through detailed process and device simulations. These MJNFETs are also ideally suited for new types of nano-architectures such as N3ASICs [5] which utilize regular nanowire arrays with limited customization. In such nano- systems, the simplified device geometry in conjunction with a single-type FET circuit style [6] would imply that logic arrays could be patterned out of pre-doped SOI wafers without the need for any additional ion implantation.
Si Nanowire - Array Source Gated Transistors  [PDF]
Charles Opoku,Radu Sporea,Vlad Stolojan,Ravi Silva,Maxim Shkunov
Physics , 2015,
Abstract: Solution processed field-effect transistors based on single crystalline silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The semiconducting layer was deposited from a nanowire ink formulation at room temperature. The devices with 230nm thick SiO2 gate insulating layers show excellent output current-voltage characteristics with early saturation voltages under 2 volts, constant saturation current and exceptionally low dependence of saturation voltage with the gate field. Operational principles of these devices are markedly different from traditional ohmic-contact field-effect transistors (FETs), and are explained using the source-gated transistor (SGT) concept in which the semiconductor under the reverse biased Schottky source barrier is depleted leading to low voltage pinch-off and saturation of drain current. Device parameters including activation energy are extracted at different temperatures and gate voltages to estimate the Schottky barrier height for different electrode materials to establish transistor performance - barrier height relationships. Numerical simulations are performed using 2D thin-film approximation of the device structures at various Schottky barrier heights. Without any adjustable parameters and only assuming low p-doping of the transistor channel, the modelled data show exceptionally good correlation with the measured data. From both experimental and simulation results, it is concluded that source-barrier controlled nanowire transistors have excellent potential advantages compared with a standard FET including mitigation of short-channel effects, insensitivity in device operating currents to device channel length variation, higher on/off ratios, higher gain, lower power consumption and higher operational speed for solution processable and printable nanowire electronics.
Dopant Implantation into the Silicon Substrate with Non-Planar Surface  [PDF]
Gennady A. Tarnavsky, Evgenii V. Vorozhtsov
Energy and Power Engineering (EPE) , 2010, DOI: 10.4236/epe.2010.22011
Abstract: The influence of technological process parameters (aiming angle and implantation energy) on the distributions of dopant concentrations in a silicon substrate is investigated by computer modeling.
Transport in Silicon Nanowires: Role of Radial Dopant Profile  [PDF]
Troels Markussen,Riccardo Rurali,Antti-Pekka Jauho,Mads Brandbyge
Physics , 2008,
Abstract: We consider the electronic transport properties of phosphorus (P) doped silicon nanowires (SiNWs). By combining ab initio density functional theory (DFT) calculations with a recursive Green's function method, we calculate the conductance distribution of up to 200 nm long SiNWs with different distributions of P dopant impurities. We find that the radial distribution of the dopants influences the conductance properties significantly: Surface doped wires have longer mean-free paths and smaller sample-to-sample fluctuations in the cross-over from ballistic to diffusive transport. These findings can be quantitatively predicted in terms of the scattering properties of the single dopant atoms, implying that relatively simple calculations are sufficient in practical device modeling
Time Resolved Single Dopant Charge Dynamics in Silicon  [PDF]
Mohammad Rashidi,Jacob Burgess,Marco Taucer,Roshan Achal,Jason L. Pitters,Sebastian Loth,Robert A. Wolkow
Physics , 2015,
Abstract: As the ultimate miniaturization of semiconductor devices approaches, it is imperative that the effects of single dopants be clarified. Beyond providing insight into function and limitations of conventional devices, such information enables identification of new device concepts. Atomically resolved, electronic pump-probe scanning tunneling microscopy permits unprecedented, quantitative measurement of time-resolved single dopant ionization dynamics. Tunneling through the surface dangling bond makes feasible what would otherwise be too weak a signal to observe. We introduce a time-resolved scanning-tunneling-spectroscopy method whereby current measurements are made before the system of study relaxes or adjusts to accommodate an applied field. Distinct ionization and neutralization rates of a single dopant are measured and the physical process controlling those are identified.
Dopant Induced Stabilization of Silicon Cluster at Finite Temperature  [PDF]
Shahab Zorriasatein,Kavita Joshi,D. G. Kanhere
Physics , 2006, DOI: 10.1103/PhysRevB.75.045117
Abstract: With the advances in miniaturization, understanding and controlling properties of significant technological systems like silicon in nano regime assumes considerable importance. It turns out that small silicon clusters in the size range of 15-20 atoms are unstable upon heating and in fact fragment in the temperature range of 1200 K to 1500 K. In the present work we demonstrate that it is possible to stabilize such clusters by introducing appropriate dopant (in this case Ti). Specifically, by using the first principle density functional simulations we show that Ti doped Si$_{16}$, having the Frank-Kasper geometry, remains stable till 2200 K and fragments only above 2600 K. The observed melting transition is a two step process. The first step is initiated by the surface melting around 600 K. The second step is the destruction of the cage which occurs around 2250 K giving rise to a peak in the heat capacity curve.
Gated Mode Superconducting Nanowire Single Photon Detectors  [PDF]
Mohsen K. Akhlaghi,A. Hamed Majedi
Physics , 2011, DOI: 10.1364/OE.20.001608
Abstract: Single Photon Detectors (SPD) are fundamental to quantum optics and quantum information. Superconducting Nanowire SPDs (SNSPD) [1] provide high performance in terms of quantum efficiency (QE), dark count rate (DCR) and timing jitter [2], but have limited maximum count rate (MCR) when operated as a free-running mode (FM) detector [3, 4]. However, high count rates are needed for many applications like quantum computing [5] and communication [6], and laser ranging [7]. Here we report the first operation of SNSPDs in a gated mode (GM) that exploits a single photon triggered latching phenomenon to detect photons. We demonstrate operation of a large active area single element GM-SNSPD at 625MHz, one order of magnitude faster than its FM counterpart. Contrary to FM-SNSPDs, the MCR in GM can be pushed to GHz range without a compromise on the active area or QE, while reducing the DCR.
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