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A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs  [PDF]
Jin Young Choi, Choongkoo Park
Circuits and Systems (CS) , 2011, DOI: 10.4236/cs.2011.23025
Abstract: We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device. The comparison study mainly focuses on robustness against the HBM ESD in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.
Discharge Characteristics of a Triple-Well Diode-String ESD Clamp  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2018, DOI: 10.4236/cs.2018.95008
Abstract: In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.
A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology  [PDF]
Chih-Yao Huang,Fu-Chien Chiu
Advances in Materials Science and Engineering , 2013, DOI: 10.1155/2013/905686
Abstract: A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case. 1. Introduction Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems. An NMOSFET has been the most popular ESD protection candidate for a long time. Since the shrinking of device size advances continually, the ESD capability of the NMOS device encounters more challenges [1–7]. A gate-grounded NMOS (GGNMOS) can no longer satisfy the ESD protection mission easily. ESD NMOS protection devices usually need the large width size to deal with ESD events. This results in multifinger layout style which is commonly used in practical IC I/O area. But it also has a critical drawback which is not favorable for the ESD protection requirement. The conduction current is usually unevenly distributed along the width direction of the multifingers. Gate-coupling technique using the property that increases the gate bias can reduce the first trigger point of the NMOS device and enable uniform ESD current distribution [4, 8, 9]. Although gate-coupling technique can improve the ESD capability, it still has gate overdriven effect if the gate voltage coupled is much larger than its threshold voltage, and this leads to serious ESD degradation. Furthermore, inserted or butting substrate pickups in the source diffusion region of the ESD NMOS device in deep submicrometer technology also degraded ESD reliability seriously. Such layout style has been strictly prohibited in practical ESD design applications by the technology design rules. Therefore, in this work, a new substrate-and-gate triggering (SGT) structure that utilizes dynamic
Design on an ESD Protection Circuit with GG-NMOS Structure in CMOS Technology
CMOS工艺中GG-NMOS结构ESD保护电路设计

Du Ming,Hao Yue,Zhu Zhiwei,
杜鸣
,郝跃,朱志炜

半导体学报 , 2005,
Abstract: An ESD protection circuit which uses a GG-NMOS structure is presented.The operating principle and test results are depicted.An improved project,gate-couple technology,on the circuit is presented,and the anticipated effect is achieved.The ability of the circuit achieves class 2 of the human-body model.It is also indicated that ESD induces damage of the gate oxide with microcosmic mechanisms,where ESD occurs based on simulation.
On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.79199
Abstract: In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDDbus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.
一种片上低触发电压高耐压NMOS ESD防护结构设计  [PDF]
陈迪平,,,,,陈思园
- , 2016,
Abstract: 设计了一种触发电压低于10 V,HBM耐压超过4 kV的低触发、高耐压NMOS ESD防护结构.通过带钳位的栅耦合RC网络来适当抬升ESD泄放管栅压与衬底电压.在提高泄放能力与降低触发电压的同时,依然保持了较高的二次击穿电流It,从而增强了MOS防护结构在深亚微米CMOS电路中的ESD防护能力.该结构最终在CSMC HJ018工艺流片,并通过TLP测试平台测得触发电压低于10 V,二次击穿电流3.5 A,达到设计要求.
This paper designed a NMOS ESD protection circuit with low trigger voltage (trigger voltage ≤10 V) and high ESD robustness (HBM ESD level≥4 kV).It raises the bias voltage of both the gate and the substrate of the main discharge element to an appropriate extent by designing a gate-coupled RC-network with voltage-clamping function.This not only provides a stronger discharge capacity and lower trigger voltage but also maintains a high secondary breakdown current.In this case, the ESD robustness of the MOS protection structure in CMOS deep submicron circuit is strengthened.The design is taped out in CSMC HJ018 process, and tested through TLP platform, which shows the trigger voltage is lower than 10 V and the secondary breakdown current is 3.5 A.
Investigation of the polysilicon p--i--n diode and diode string as a process compatible and portable ESD protection device
多晶PIN二极管及二极管串作良好工艺兼容并可移植ESD保护器件的研究

Jiang Yibo,Du Huan,Han Zhengsheng,
姜一波
,杜寰,韩郑生

半导体学报 , 2012,
Abstract: The polysilicon p-i-n diode displayed noticeable process-compatibility and portability in advance technologies as ESD protection device. The paper presented reverse breakdown, current leakage and capacitance characteristics for the fabricated polysilicon p-i-n diode. To evaluate ESD robustness forward and reverse TLP I-V characteristics were measured also. Besides polysilicon p-i-n diode string was investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. To explain the effects of device parameter, analysis and discussion about the inherent properties of polysilicon p-i-n diode were processed finally.
Linearity Improvement of Cascode Cmos Lna Using a Diode Connected Nmos Transistor with a Parallel RC Circuit
Chieh-Pin Chang;Wei-Chih Chien;Chun-Chi Su;Yeong-Her Wang;Ja-Hao Chen
PIER C , 2010, DOI: 10.2528/PIERC10082411
Abstract: A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6 mA from a 1.8 V power supply.
Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13- m silicide CMOS technology
0.13微米硅化物 CMOS工艺下版图参数对栅极接地 NMOS晶体管骤回特性的影响

Jiang Yuxi,Li Jiao,Ran Feng,Cao Jialin,Yang Dianxiong,
姜玉稀
,李娇,冉峰,曹家麟,杨殿雄

半导体学报 , 2009,
Abstract: 本文中,在 0.13微米硅化物 CMOS工艺下, 设计了不同版图尺寸和不同版图布局的栅极接地 NMOS器件。TLP测量技术用来获得器件的骤回特性。 文章分析了器件版图参数和器件骤回特性之间的关系。TCAD器件仿真软件被用来解释证明这些结论.通过这些结论,电路设计者可以预估栅极接地NMOS器件在ESD大电流情况下的特性,由此在有限的版图面积下设计符合 ESD保护要求的栅极接地 NMOS器件。本文同时给出了优化后的 0.13微米硅化物工艺下 ESD版图规则。
ESD and Its Related Mechanisms on LDD-CMOS
LDD-CMOS中ESD及其相关机理

Ma Wei,Hao Yue,
马巍
,郝跃

半导体学报 , 2003,
Abstract: LDD is widely used in sub half micrometer CMOS VLSI.Due to its improvement of the distribution of electrical field in channel,the effect of high field near the drain is reduced.Consequently,the life of hot carrier of the circuits and devices is prolonged in the aspect of reliability.However,LDD has a poor performance against ESD stress.A research has been made on the latent damages under the influences of snapback.And special attention is given to the correlation with hot carrier in LDD gg nMOS during ESD events.
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