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Linear Approach for Synchronous State Stability in Fully Connected PLL Networks
José R. C. Piqueira,Maurízio Q. de Oliveira,Luiz H. A. Monteiro
Mathematical Problems in Engineering , 2008, DOI: 10.1155/2008/364084
Abstract: Synchronization is an essential feature for the use of digital systems in telecommunication networks, integrated circuits, and manufacturing automation. Formerly, master-slave (MS) architectures, with precise master clock generators sending signals to phase-locked loops (PLLs) working as slave oscillators, were considered the best solution. Nowadays, the development of wireless networks with dynamical connectivity and the increase of the size and the operation frequency of integrated circuits suggest that the distribution of clock signals could be more efficient if distributed solutions with fully connected oscillators are used. Here, fully connected networks with second-order PLLs as nodes are considered. In previous work, how the synchronous state frequency for this type of network depends on the node parameters and delays was studied and an expression for the long-term frequency was derived (Piqueira, 2006). Here, by taking the first term of the Taylor series expansion for the dynamical system description, it is shown that for a generic network with nodes, the synchronous state is locally asymptotically stable.
Comments on "IEEE 1588 Clock Synchronization using Dual Slave Clocks in a Slave"  [PDF]
Kyeong Soo Kim
Computer Science , 2014, DOI: 10.1109/LCOMM.2014.2317738
Abstract: In the above letter, Chin and Chen proposed an IEEE 1588 clock synchronization method based on dual slave clocks, where they claim that multiple unknown parameters --- i.e., clock offset, clock skew, and master-to-slave delay --- can be estimated with only one-way time transfers using more equations than usual. This comment investigates Chin and Chen's dual clock scheme with detailed models for a master and dual slave clocks and shows that the formulation of multi-parameter estimation is invalid, which affirms that it is impossible to distinguish the effect of delay from that of clock offset at a slave even with dual slave clocks.
Implementations of DPDE for Delay Locked Loop for High Frequency Clock of 2.5GHz High Speed Applications  [PDF]
J.Meenakshi,G. Rakesh Chowdary,A.L.G.N.Aditya
International Journal of Soft Computing & Engineering , 2012,
Abstract: Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Variable delay elements have many applications in VLSI circuits. They are extensively used in digital delay locked loops phase locked loops (PLLs), digitally controlled oscillators (DCOs), and microprocessor and memory circuits. In all these circuits, the variable delay element is one of the key building blocks. Its precision directly affects the overall performance of the circuit. In this a new proposed digitally controlled delay element is implemented in 130nm technology for DLL Delay locked loop for higher clock rates greater than 2.5GHz. This is implemented in Micro wind tool.
Design and Functional Verification of A SPI Master Slave Core Using System Veilog
K.Aditya,M.Sivakumar,Fazal Noorbasha,T.Praveen Blessington
International Journal of Soft Computing & Engineering , 2012,
Abstract: Synchronous serial interfaces are widely used to provide economical board level interfaces between different devices such as microcontrollers, DACs ADCs and other. Many IC manufacturers produce components that are compatible with SPI and Microwire/plus. The SPI Master core is compatible with both protocols as master with some additional functionality. At the hosts side,the core acts like a Wishbone compliant slave device. The SPI master core consists of three parts, Serial interface, clock generator and Wishbone interface. The SPI core has five 32-bit registers through the Wishbone compatible interface. The serial interface consists of slave select lines, serial clock lines, as well as input and output data lines. All transfers are full duplex transfers of a programmable number of bits per transfer(upto 64 bits).It has 8 slave select lines but only one is selected at a time. We design the SPI Master-Slave core design using system verilog and do functional verification for our design in modelsim.
"Master and Slave" fluidic amplifier cascade  [cached]
Tesa? Václav
EPJ Web of Conferences , 2012, DOI: 10.1051/epjconf/20122501093
Abstract: No-moving-part fluidics recently found interesting application in generation of gas microbubbles by oscillating the inlet flow of the gas into the aerator. The oscillation frequency has to be high and this calls for small size of the oscillator. On the other hand, most microbubble applications require a large total gas flow. This calls for large fluidic device – a les expensive alternative than “numbering up” (several oscillators in parallel). The contradiction of the large and small scale is solved by the “MASTER & SLAVE” fluidic circuit: large output device controlled by a small oscillator. Paper discusses basic problems encountered in designing the circuit which requires matching the characteristics of the two devices.
Clock synchronization technique according to precision time protocol
基于精密时间协议的时钟同步技术

LIN Tao,ZHANG Hao,SUN He-xu,
林涛
,张浩,孙鹤旭

计算机应用 , 2007,
Abstract: The Precision Time Protocol (PTP) of the IEEE 1588 protocol provides an effective technique to synchronize the master clock and the slave clock. Collect and process the time stamp in network drives based on PTP, then synchronize the master and slave clock by using the best master clock algorithm programmed in Java and C language. Allan variance was used to describe properties of the clock.
Master–Slave double–scroll circuit incomplete synchronization  [PDF]
I. M. Kyprianidis,Ch. K. Volos,S. G. Stavrinides,I. N. Stouboulos
Journal of Engineering Science and Technology Review , 2010,
Abstract: The experimental study of the route from synchronization to desynchronization of a master-slave configuration of doublescrollcircuits, is presented. The parameter controlling the system synchronization was the coupling resistance between themaster-slave circuits. In the region between synchronization-desynchronization, it was shown that an intermediate regimeof incomplete synchronization emerged. The study of the related dynamics proved that this incomplete synchronization wasof the on-off intermittency kind.
Collection of Master-Slave Synchronized Chaotic Systems  [PDF]
A. I. Lerescu,N. Constandache,S. Oancea,I. Grosu
Physics , 2004, DOI: 10.1016/j.chaos.2004.02.039
Abstract: In this work the open-plus-closed-loop (OPCL) method of synchronization is used in order to synchronize the systems from the Sprott's collection of the simplest chaotic systems. The method is general and we were looking for the simplest coupling between master and slave system. The interval of parameters were synchronization is achieved are obtained analytically using Routh-Hurwitz conditions. Detailed calculations and numerical simulation are given for the system I from the Sprott's collection. Working in the same manner for non-linear systems based on ordinary differential equations the method can be adopted for the teaching of the topic.
Super persistent transient in a master-slave configuration with Colpitts oscillators  [PDF]
R. C. Bonetti,S. L. T. de Souza,A. M. Batista,J. D. Szezech Jr.,I. L. Caldas,R. L. Viana,S. R. Lopes,M. S. Baptista
Physics , 2014, DOI: 10.1088/1751-8113/47/40/405101
Abstract: Master-slave systems have been intensively investigated to model the application of chaos to communications. We considered Colpitts oscillators coupled according to a master-slave configuration to study chaos synchronisation. We revealed the existence of super persistent transients in this coupled system. Moreover, we showed that an additive noise added to the slave system may suppress chaos synchronisation. When synchronisation is not suppressed, the noise induces longer transients.
Phase-coherent repetition rate multiplication of a mode-locked laser from 40 MHz to 1 GHz by injection locking  [PDF]
D. Kielpinski,O. Gat
Physics , 2011, DOI: 10.1364/OE.20.002717
Abstract: We have used injection locking to multiply the repetition rate of a passively mode-locked femtosecond fiber laser from 40 MHz to 1 GHz while preserving optical phase coherence between the master laser and the slave output. The system is implemented almost completely in fiber and incorporates gain and passive saturable absorption. The slave repetition rate is set to a rational harmonic of the master repetition rate, inducing pulse formation at the least common multiple of the master and slave repetition rates.
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