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Exploiting the full potential of photometric quasar surveys: Optimal power spectra through blind mitigation of systematics  [PDF]
Boris Leistedt,Hiranya V. Peiris
Physics , 2014, DOI: 10.1093/mnras/stu1439
Abstract: We present optimal measurements of the angular power spectrum of the XDQSOz catalogue of photometric quasars from the Sloan Digital Sky Survey. These measurements rely on a quadratic maximum likelihood estimator that simultaneously measures the auto- and cross-power spectra of four redshift samples, and provides minimum-variance, unbiased estimates even at the largest angular scales. Since photometric quasars are known to be strongly affected by systematics such as spatially-varying depth and stellar contamination, we introduce a new framework of extended mode projection to robustly mitigate the impact of systematics on the power spectrum measurements. This technique involves constructing template maps of potential systematics, decorrelating them on the sky, and projecting out modes which are significantly correlated with the data. Our method is able to simultaneously process several thousands of nonlinearly-correlated systematics, and mode projection is performed in a blind fashion. Using our final power spectrum measurements, we find a good agreement with theoretical predictions, and no evidence for further contamination by systematics. Extended mode projection not only obviates the need for aggressive sky and quality cuts, but also provides control over the level of systematics in the measurements, enabling the search for small signals of new physics while avoiding confirmation bias.
Enhancing Wireless Information and Power Transfer by Exploiting Multi-Antenna Techniques  [PDF]
Xiaoming Chen,Zhaoyang Zhang,Hsiao-Hwa Chen,Huazi Zhang
Mathematics , 2015,
Abstract: This paper reviews emerging wireless information and power transfer (WIPT) technique with an emphasis on its performance enhancement employing multi-antenna techniques. Compared to traditional wireless information transmission, WIPT faces numerous challenges. First, it is more susceptible to channel fading and path loss, resulting in a much shorter power transfer distance. Second, it gives rise to the issue on how to balance spectral efficiency for information transmission and energy efficiency for power transfer in order to obtain an optimal tradeoff. Third, there exists a security issue for information transmission in order to improve power transfer efficiency. In this context, multi-antenna techniques, e.g., energy beamforming, are introduced to solve these problems by exploiting spatial degree of freedom. This article provides a tutorial on various aspects of multi-antenna based WIPT techniques, with a focus on tackling the challenges by parameter optimization and protocol design. In particular, we investigate the WIPT tradeoffs based on two typical multi-antenna techniques, namely limited feedback multi-antenna technique for short-distance transfer and large-scale multiple-input multiple-output (LS-MIMO, also known as massive MIMO) technique for long-distance transfer. Finally, simulation results validate the effectiveness of the proposed schemes.
Exploiting Known Interference as Green Signal Power for Downlink Beamforming Optimization  [PDF]
C. Masouros,G. Zheng
Mathematics , 2015,
Abstract: We propose a data-aided transmit beamforming scheme for the multi-user multiple-input-single-output (MISO) downlink channel. While conventional beamforming schemes aim at the minimization of the transmit power subject to suppressing interference to guarantee quality of service (QoS) constraints, here we use the knowledge of both data and channel state information (CSI) at the transmitter to exploit, rather than suppress, constructive interference. More specifically, we design a new precoding scheme for the MISO downlink that minimizes the transmit power for generic phase shift keying (PSK) modulated signals. The proposed precoder reduces the transmit power compared to conventional schemes, by adapting the QoS constraints to accommodate constructive interference as a source of useful signal power. By exploiting the power of constructively interfering symbols, the proposed scheme achieves the required QoS at lower transmit power. We extend this concept to the signal to interference plus noise ratio (SINR) balancing problem, where higher SINR values compared to the conventional SINR balancing optimization are achieved for given transmit power budgets. In addition, we derive equivalent virtual multicast formulations for both optimizations, both of which provide insights of the optimal solution and facilitate the design of a more efficient solver. Finally, we propose a robust beamforming technique to deal with imperfect CSI, that also reduces the transmit power over conventional techniques, while guaranteeing the required QoS. Our simulation and analysis show significant power savings for small scale MISO downlink channels with the proposed data-aided optimization compared to conventional beamforming optimization.
AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN
Praveer Saxena,Prof. Dinesh Chandra,Sampath Kumar V
International Journal on Computer Science and Engineering , 2011,
Abstract: Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using several adiabatic logic styles, which are derived from static CMOS logic, without a large change. The full adders are designed using 180nm technology parameters provided by predictive technology and simulated using HSPICE. The full adders designed are compared in terms of average power consumption with different values of load capacitance, temperature and input frequency. The different designs of full adder are also compared on the basis of propagation delay exhibit by them. It is found that, full adders designed with adiabatic logic styles tends to consume very low power in comparison to full adder designed with static CMOS logic. Under certain operating conditions, one of adiabatic designs of full adder achieves upto 74% power saving in comparison to the full adder designedwith static CMOS logic.
Power Splitting for Full-Duplex Relay with Wireless Information and Power Transfer  [PDF]
Hongwu Liu,Kyeong Jin Kim,Kyung Sup Kwak
Mathematics , 2015,
Abstract: This paper investigates power splitting for full-duplex relay networks with wireless information and energy transfer. By applying power splitting as a relay transceiver architecture, the full duplex information relaying can be powered by energy harvested from the source-emitted radio frequency signal. In order to minimize outage probability, power splitting ratios have been dynamically optimized according to full channel state information (CSI) and partial CSI, respectively. Under strong loop interference, the proposed full CSI-based and partial CSI-based power splitting schemes achieve the better outage performance than the fixed power splitting scheme, whereas the partial CSI-based power splitting scheme can ensure competitive outage performance without requiring CSI of the second-hop link. It is also observed that the worst outage performance is achieved when the relay is located midway between the source and destination, whereas the outage performance of partial CSI-based power splitting scheme approaches that of full CSI-based scheme when the relay is placed close to the destination.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITS  [PDF]
Y. Sunil Gavaskar Reddy,V.V.G.S.Rajendra Prasad
International Journal of VLSI Design & Communication Systems , 2011,
Abstract: Full adders are important components in applications such as digital signal processors (DSP)architectures and microprocessors. Apart from the basic addition adders also used in performing usefuloperations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paperconventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits areanalyzed in terms of power and transistor count using 0.18UM technology.
Power comparison of CMOS and adiabatic full adder circuit  [PDF]
Sunil Gavaskar Reddy,Rajendra prasad
Computer Science , 2011, DOI: 10.5121/vlsic.2011.2306
Abstract: Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic  [PDF]
V. A. Bartlett,E. Grass
VLSI Design , 2001, DOI: 10.1155/2001/94037
Abstract: Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.
Exploiting the full power of temporal gene expression profiling through a new statistical test: Application to the analysis of muscular dystrophy data
Veronica Vinciotti, Xiaohui Liu, Rolf Turk, Emile J de Meijer, Peter AC 't Hoen
BMC Bioinformatics , 2006, DOI: 10.1186/1471-2105-7-183
Abstract: We validate the temporal Hotelling T2-test on muscular gene expression data from four mouse strains which were profiled at different ages: dystrophin-, beta-sarcoglycan and gamma-sarcoglycan deficient mice, and wild-type mice. The first three are animal models for different muscular dystrophies. Extensive biological validation shows that the method is capable of finding genes with temporal profiles significantly different across the four strains, as well as identifying potential biomarkers for each form of the disease. The added value of the temporal test compared to an identical test which does not make use of temporal ordering is demonstrated via a simulation study, and through confirmation of the expression profiles from selected genes by quantitative PCR experiments. The proposed method maximises the detection of the biologically interesting genes, whilst minimising false detections.The temporal Hotelling T2-test is capable of finding relatively small and robust sets of genes that display different temporal profiles between the conditions of interest. The test is simple, it can be used on gene expression data generated from any experimental design and for any number of conditions, and it allows fast interpretation of the temporal behaviour of genes. The R code is available from V.V. The microarray data have been submitted to GEO under series GSE1574 and GSE3523.In a typical time course microarray study, a number of microarray experiments are carried out at biologically interesting time points and across different biological conditions. It is a frequent and challenging goal to try to identify which of these genes exhibit an interesting temporal behaviour, for example whether and when a gene becomes up- or down-regulated and, more importantly, whether its behaviour is significantly different across the biological conditions of interest.Various methods have been proposed in the literature to detect differentially expressed genes from time course microarray experime
Power and Delay Comparison in between Different types of Full Adder Circuits
SARADINDU PANDA,A.BANERJEE, B.MAJI,DR. A.K.MUKHOPADHYAY
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering , 2013,
Abstract: This paper describes the speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. Power consumption and speed are two important but conflicting design aspects; hence a better metric to evaluate circuit performance is power delay product (PDP).The driving capability of a full adder is very important, because, full adders are mostly used in cascade configuration, where the output of one provides the input for other. If the full adders lack driving capability then it requires additional buffer, which consequently increases the power dissipation. Here, we have given a brief description of the evolution of full adder circuits in terms of lesser power consumption, higher speed and lesser chip size. We have started with the most conventional 28 transistor full adder and then gradually studied full adders consisting of as less as 8 transistors. We have also included some of the most popular full adder cells like Static Energy Recovery Full Adder (SERF) [7] [8], Adder9A, Adder9B, GDI based full adder.
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