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Processor-Dependent Malware... and codes  [PDF]
Anthony Desnos,Robert Erra,Eric Filiol
Computer Science , 2010,
Abstract: Malware usually target computers according to their operating system. Thus we have Windows malwares, Linux malwares and so on ... In this paper, we consider a different approach and show on a technical basis how easily malware can recognize and target systems selectively, according to the onboard processor chip. This technology is very easy to build since it does not rely on deep analysis of chip logical gates architecture. Floating Point Arithmetic (FPA) looks promising to define a set of tests to identify the processor or, more precisely, a subset of possible processors. We give results for different families of processors: AMD, Intel (Dual Core, Atom), Sparc, Digital Alpha, Cell, Atom ... As a conclusion, we propose two {\it open problems} that are new, to the authors' knowledge.
GOLGI: un cluster Opteron per il CILEA  [cached]
Claudio Arlandini
Bollettino del CILEA , 2006, DOI: 10.1472/bc.v101i0.1244
Abstract: Il CILEA potenzia il suo parco macchine per il calcolo parallelo a alte prestazioni con un cluster di 55 nodi AMD Opteron, fornito dalla Exadron, Divisione High Performance Computing di Eurotech Spa. Con questa acquisizione il CILEA diversifica la sua offerta nel campo delle macchine a memoria distribuita. CILEA is strengthening its role in High Performance Computing with a new 55 AMD Opteron nodes cluster, provided by Exadron, High Performance Computing Division of Eurotech Spa. The acquisition is meant to diversify its distributed memory machines offer to customers.
Performance Scaling of Individual SPEC INT 2006 Results for AMD Processors
Abdul KAREEM P.,R. A. SINGH
Leonardo Electronic Journal of Practices and Technologies , 2009,
Abstract: High performance is a critical requirement to all microprocessors manufacturers. In this paper we describe the performance scaling trends in AMD Opteron 2000+ and AMD Opteron 8000+ series processors. The micro architecture of these processors is implemented using the basis of a new family of processors to AMD x86-64 processors. These processors can provide a performance boost for many key application areas in modern generation. We analyze the scaling of performance in two major series of AMD processors (AMD Opteron 2000+ and AMD Opteron 8000+ Series) by using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. Our results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.
Cell processor implementation of a MILC lattice QCD application  [PDF]
Guochun Shi,Volodymyr Kindratenko,Steven Gottlieb
Physics , 2009,
Abstract: We present results of the implementation of one MILC lattice QCD application-simulation with dynamical clover fermions using the hybrid-molecular dynamics R algorithm-on the Cell Broadband Engine processor. Fifty-four individual computational kernels responsible for 98.8% of the overall execution time were ported to the Cell's Synergistic Processing Elements (SPEs). The remaining application framework, including MPI-based distributed code execution, was left to the Cell's PowerPC processor. We observe that we only infrequently achieve more than 10 GFLOPS with any of the kernels, which is just over 4% of the Cell's peak performance. At the same time, many of the kernels are sustaining a bandwidth close to 20 GB/s, which is 78% of the Cell's peak. This indicates that the application performance is limited by the bandwidth between the main memory and the SPEs. In spite of this limitation, speedups of 8.7x (for 8x8x16x16 lattice) and 9.6x (for 16x16x16x16 lattice) were achieved when comparing a 3.2 GHz Cell processor to a single core of a 2.33 GHz Intel Xeon processor. When comparing the code scaled up to execute on a dual-Cell blade and a quad-core dual-chip Intel Xeon blade, the speedups are 1.5x (8x8x16x16 lattice) and 4.1x (16x16x16x16 lattice).
A Detailed Comparison of NLO QCD Evolution Codes  [PDF]
J. Blümlein,M. Botje,C. Pascaud,S. Riemersma,W. L. van Neerven,A. Vogt,F. Zomer
Physics , 1996,
Abstract: Seven next-to-leading order QCD evolution programs are compared. The deviations of the results due to different theoretical prescriptions for truncating the perturbative series are clarified, and a numerical agreement between five codes of better than 0.1% is achieved. Reference results for further comparison are provided.
基于AMD64位处理器工作站HP Workstation xw 9300
中国图象图形学报 , 2005,
Abstract: 近日,HP发布了旗下个人工作站家族新成员——HP workstation xw9300。作为HP工作站家族中第一款采用AMD处理器的产品,HP xw 9300也是实现了支持双AMD Opteron 64位处理器和双PCI-Express x16图形卡的高性能工作站。基于AMD Opteron64位处理器在高性能计算领域的优异表现,以及NVIDIA所提供的业界领先的图形卡技术,HP xw 9300为用户带来了更出色的计算性能和更强大的图形处理能力。
Nuovi compilatori e librerie matematiche
Maurizio Cremonesi
Bollettino del CILEA , 2007, DOI: 10.1472/bc.v105i0.1326
Abstract: L’ambiente applicativo dei cluster Intel/Xeon e AMD/Opteron è stato completato nei primi mesi di quest’anno con strumenti di sviluppo che permettono di installare i programmi nella modalità più efficiente possibile. The program environment of the Intel/Xeon and AMD/Opteron clusters has been enriched within the first months of this year with developing software instruments that enable the installation of fast and reliable codes.
Portable QCD codes for Massively Parallel Processors. UKQCD collaboration  [PDF]
Nick Stanford
Physics , 1993,
Abstract: We present a new set of QCD codes in both message passing and data parallel versions. The message passing package used is PARMACS, although other packages may be used. Data parallel software is written in High Performance fortran, an emerging standard based on Fortran 90. Software engineering methods have been applied to a physics application to create thoroughly tested and documented codes for the next generation of massively parallel supercomputers.
A Linux PC cluster for lattice QCD with exact chiral symmetry  [PDF]
Ting-Wai Chiu,Tung-Han Hsieh,Chao-Hsi Huang,Tsung-Ren Huang
Physics , 2002, DOI: 10.1142/S0129183103004954
Abstract: A computational system for lattice QCD with exact chiral symmetry is described. The platform is a home-made Linux PC cluster, built with off-the-shelf components. At present this system constitutes of 64 nodes, with each node consisting of one Pentium 4 processor (1.6/2.0/2.5 GHz), one Gbyte of PC800/PC1066 RDRAM, one 40/80/120 Gbyte hard disk, and a network card. The computationally intensive parts of our program are written in SSE2 codes. The speed of this system is estimated to be 70 Gflops, and its price/performance is better than $1.0/Mflops for 64-bit (double precision) computations in quenched QCD. We discuss how to optimize its hardware and software for computing quark propagators via the overlap Dirac operator.
Performance of a Lattice Quantum Chromodynamics Kernel on the Cell Processor  [PDF]
J. Spray,J. Hill,A. Trew
Physics , 2008, DOI: 10.1016/j.cpc.2008.06.006
Abstract: The implementation of a proof-of-concept Lattice Quantum Chromodynamics kernel on the Cell processor is described in detail, illustrating issues encountered in the porting process. The resulting code performs up to 45GFlop/s per socket, indicating that the Cell processor is likely to be a good platform for future Lattice QCD calculations.
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