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In-Field Logic Repair of Deep Sub-Micron CMOS Processors  [PDF]
Massoud Mokhtarpour Ghahroodi,Mark Zwolinski
Computer Science , 2015, DOI: 10.13140/RG.2.1.2435.6566
Abstract: Ultra Deep-Sub-Micron CMOS chips have to function correctly and reliably, not only during their early post-fabrication life, but also for their entire life span. In this paper, we present an architectural-level in-field repair technique. The key idea is to trade area for reliability by adding repair features to the system while keeping the power and the performance overheads as low as possible. In the case of permanent faults, spare blocks will replace the faulty blocks on the fly. Meanwhile by shutting down the main logic blocks, partial threshold voltage recovery can be achieved which will alleviate the ageing-related delays and timing issues. The technique can avoid fatal shut-downs in the system and will decrease the down-time, hence the availability of such a system will be preserved. We have implemented the proposed idea on a pipelined processor core using a conventional ASIC design flow. The simulation results show that by tolerating about 70% area overhead and less than 18% power overhead we can dramatically increase the reliability and decrease the downtime of the processor.
NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates  [PDF]
Ali Dadashi, Omid Mirmotahari, Yngvar Berg
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.78166
Abstract: In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED  [PDF]
Sreenivasa Rao.Ijjada,Ayyanna.G,G.Sekhar Reddy,Dr.V.Malleswara Rao
International Journal of VLSI Design & Communication Systems , 2011,
Abstract: Designing high-speed low-power circuits with CMOS technology has been a major research problem formany years. Several logic families have been proposed and used to improve circuit performance beyondthat of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicrontechnologies since the performance benefits obtained from process scaling are decreasing as feature sizedecreases. This paper presents CMOS differential circuit families such as Dual rail domino logic andpseudo Nmos logic their delay and power variations in terms of adder design and logical design. DominoCMOS has become the prevailing logic family for high performance CMOS applications and it isextensively used in most state-of-the-art processors due to its high speed capabilities. The drawback ofdomino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-RailDomino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output aregenerated, provides a robust solution to this problem.
Reliability and Fault Tolerance of Ultra Low Voltage High Speed Differential CMOS
Omid Mirmotahari,Yngvar Berg
Lecture Notes in Engineering and Computer Science , 2009,
Abstract:
Speed and Reliability of Nanomagnetic Logic Technology  [PDF]
Zheng Gu,Mark E. Nowakowski,David B. Carlton,Ralph Storz,Jeongmin Hong,Weilun Chao,Brian Lambson,Patrick Bennett,Mohmmad T. Alam,Matthew A. Marcus,Andrew Doran,Anthony Young,Andreas Scholl,Jeffrey Bokor
Physics , 2014,
Abstract: Nanomagnetic logic is an energy efficient computing architecture that relies on the dipole field coupling of neighboring magnets to transmit and process binary information. In this architecture, nanomagnet chains act as local interconnects. To assess the merits of this technology, the speed and reliability of magnetic signal transmission along these chains must be experimentally determined. In this work, time-resolved pump-probe x-ray photo-emission electron microscopy is used to observe magnetic signal transmission along a chain of nanomagnets. We resolve successive error-free switching events in a single nanomagnet chain at speeds on the order of 100 ps per nanomagnet, consistent with predictions based on micromagnetic modeling. Errors which disrupt transmission are also observed. We discuss the nature of these errors, and approaches for achieving reliable operation.
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design  [PDF]
Subodh Wairya,Rajendra Kumar Nagaria,Sudarshan Tiwari
VLSI Design , 2012, DOI: 10.1155/2012/173079
Abstract: This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC?0.18? m process models in Cadence Virtuoso Schematic Composer at 1.8?V single-ended supply voltage, and simulations are carried out on Spectre S. 1. Introduction It is time we explore the well-engineered deep submicron CMOS technologies to address the challenging criteria of these emerging low-power and high-speed communication digital signal processing chips. The performance of many applications as digital signal processing depends upon the performance of the arithmetic circuits to execute complex algorithms such as convolution, correlation, and digital filtering. Fast arithmetic computation cells including adders and multipliers are the most frequently and widely used circuits in very-large-scale integration (VLSI) systems. The semiconductor industry has witnessed an explosive growth of integration of sophisticated multimedia-based applications into mobile electronics gadgetry since the last decade. However, the critical concern in this arena is to reduce the increase in power consumption beyond a certain range of operating frequency. Moreover, with the explosive growth, the demand, and the popularity of portable electronic products, the designers are driven to strive for smaller silicon area, higher speed, longer battery life, and enhanced reliability. The XOR-XNOR circuits are basic building blocks in various circuits especially arithmetic circuits (adders & multipliers), compressors, comparators, parity checkers, code converters, error-detecting or
Sub-threshold Logic for Ultra-Low Power Consumption
Isha Arora
International Journal of Technological Exploration and Learning , 2013,
Abstract: In the ultra low power end of design spectrum when performance is of secondary importance, digital subthreshold logic circuits are more applicable than the regular MOS logic. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both these logic families have comparable power consumption as regular subthreshold CMOS logic along with superior robustness and tolerance to process and temperature variations.
Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS  [PDF]
David Bol
Journal of Low Power Electronics and Applications , 2011, DOI: 10.3390/jlpea1010001
Abstract: Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.
Low-voltage MOS Current Mode Logic for Low-Power and High Speed Applications  [PDF]
Yangbo Wu,Jianping Hu
Information Technology Journal , 2011,
Abstract: Low power design has already become the main challenge in the modern VLSI design community. The voltage scaling techniques have proved one of the most effective methods for low power design. In this study, the design method of the low-voltage low-power MOS Current-Mode Logic (MCML) in nanometer CMOS technology is addressed. The analytical formulation of minimum supply voltage of the two-level MCML is derived. The results show that the power consumption in MCML can be decreased by reducing the supply voltage VDD without degrading the performance of MCML. As examples, the low-voltage MCML 1-bit full adder and 4-2 compressor are designed and simulated by HSPICE at the 45 nm CMOS process using the NCSU PTM model. The simulation results show that the proposed 1-bit full adder can obtained about 36 and 31% energy savings compared with the conventional MCML and CMOS ones using normal supply voltage at 4.0 GHz, respectively. The low-voltage MCML 4-2 compressor based on full adders can obtained about 33% energy savings compared with the conventional CMOS one at 5.0 GHz.
Geometry Effects in Switching of Nanomagnets with Strain: Reliability, Energy Dissipation and Clock Speed in Dipole-Coupled Nanomagnetic Logic  [PDF]
Md Mamun Al-Rashid,Jayasimha Atulasimha,Supriyo Bandyopadhyay
Physics , 2014,
Abstract: Strain-clocked dipole coupled nanomagnetic logic promises significant advancement in the search for an energy-efficient Boolean logic paradigm. However, the issue of high error rates remains a daunting obstacle. This work presents a comprehensive quantitative comparison between the two most studied nanomagnetic logic device geometries (elliptical and cylindrical) and current CMOS logic switches in terms of reliability, energy dissipation and clock speed. We had previously reported that the out-of-plane excursion of the magnetization vector during switching creates a precessional torque that is responsible for high switching error probability in elliptical nanomagnet geometries. The absence of this torque in cylindrical geometry due to circular symmetry promises higher reliability, but also lowers the clock speed when compared with elliptical geometry. Furthermore, we show that we can obtain relatively high reliability (switching error probability < 10^-8), moderate clock speed (~ 100 MHz) and 2-3 orders of magnitude energy saving compared to CMOS devices, using dipole coupled nanomagnetic logic devices of elliptical geometry when the shape anisotropy energy barrier of the magnet is increased to ~3 eV to allow strong dipole coupling between neighboring magnets.
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