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HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture  [PDF]
Alexander Thomas,Michael Rückauer,Jürgen Becker
International Journal of Reconfigurable Computing , 2012, DOI: 10.1155/2012/832531
Abstract: Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution. 1. Introduction Reconfigurable architectures aim to reach the performance and energy-efficiency of application-specific integrated circuits while the flexibility is increased, therefore closing the gap between ASICs and general-purpose processors. For data-oriented applications an increase in performance compared to general-purpose processors can be reached by mapping operations to a possibly large set of functional units, which are working in parallel. In contrast to ASICs, their actual function and the interconnection between the units are not determined during design and manufacturing but may be changed at runtime to support a wider range of applications. For example, in a mesh-based architecture, a flexible communication network connects the functional units (FUs) on demand. Since the FUs are communicating directly by exchanging the intermediate results through the communication network, memory accesses for temporary data storage are avoided and memory bandwidth usage is reduced to a minimum. The overall data throughput is at maximum and very close to the ideal performance that can be reached by ASIC implementations. However, this approach is not without limitations. The increased flexibility comes at the cost of additional hardware. The flexible communication network for FUs requires a lot of multiplexers, communication lines, configuration registers, and additional logic to control the configuration mechanisms. Depending on the type of the reconfigurable approach (coarse-grained or fine-grained) the overhead of the configuration registers and control logic can be considerable. An example for this fact is given by field-programmable gate arrays (FPGAs) [1, 2], which require a
A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams  [cached]
Mühlbauer Felix,Bobda Christophe
EURASIP Journal on Embedded Systems , 2006,
Abstract: This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.
A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams  [cached]
Felix Mühlbauer,Christophe Bobda
EURASIP Journal on Embedded Systems , 2006, DOI: 10.1155/es/2006/82564
Abstract: This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.
A Self-Reconfigurable Computing Platform Hardware Architecture  [PDF]
Andreas Weisensee,Darran Nathan
Computer Science , 2004,
Abstract: Field Programmable Gate Arrays (FPGAs) have recently been increasingly used for highly-parallel processing of compute intensive tasks. This paper introduces an FPGA hardware platform architecture that is PC-based, allows for fast reconfiguration over the PCI bus, and retains a simple physical hardware design. The design considerations are first discussed, then the resulting system architecture designed is illustrated. Finally, experimental results on the FPGA resources utilized for this design are presented.
Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications  [cached]
Liang Ying-Chang,Naveen Sayed,Pilakkat Santosh K.,Marath Ashok K.
EURASIP Journal on Wireless Communications and Networking , 2005,
Abstract: This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP) -based communication systems, including orthogonal frequency-division multiplexing (OFDM), single-carrier cyclic-prefix (SCCP) system, multicarrier (MC) code-division multiple access (MC-CDMA), MC direct-sequence CDMA (MC-DS-CDMA), CP-based CDMA (CP-CDMA), and CP-based direct-sequence CDMA (CP-DS-CDMA). A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.
Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications  [cached]
Liang Ying-Chang,Naveen Sayed,Pilakkat Santosh K,Marath Ashok K
EURASIP Journal on Wireless Communications and Networking , 2005,
Abstract: This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP) -based communication systems, including orthogonal frequency-division multiplexing (OFDM), single-carrier cyclic-prefix (SCCP) system, multicarrier (MC) code-division multiple access (MC-CDMA), MC direct-sequence CDMA (MC-DS-CDMA), CP-based CDMA (CP-CDMA), and CP-based direct-sequence CDMA (CP-DS-CDMA). A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.
Reconfigurable Parallel Data Flow Architecture  [PDF]
Hamid Reza Naji
Computer Science , 2010,
Abstract: This paper presents a reconfigurable parallel data flow architecture. This architecture uses the concepts of multi-agent paradigm in reconfigurable hardware systems. The utilization of this new paradigm has the potential to greatly increase the flexibility, efficiency, expandability of data flow systems and to provide an attractive alternative to the current set of disjoint approaches that are currently applied to this problem domain. The ability of methodology to implement data flow type processing with different models is presented in this paper.
Technique(s) for Spike - Sorting  [PDF]
Christophe Pouzat
Physics , 2004,
Abstract: Spike-sorting techniques attempt to classify a series of noisy electrical waveforms according to the identity of the neurons that generated them. Existing techniques perform this classification ignoring several properties of actual neurons that can ultimately improve classification performance. In this chapter, after illustrating the spike-sorting problem with real data, we propose a more realistic spike train generation model. It incorporates both a description of "non trivial" (ie, non Poisson) neuronal discharge statistics and a description of spike waveform dynamics (eg, the events amplitude decays for short inter-spike intervals). We show that this spike train generation model is analogous to a one-dimensional Potts spin glass model. We can therefore use the computational methods which have been developed in fields where Potts models are extensively used. These methods are based on the construction of a Markov Chain in the space of model parameters and spike train configurations, where a configuration is defined by specifying a neuron of origin for each spike. This Markov Chain is built such that its unique stationary density is the posterior density of model parameters and configurations given the observed data. A Monte Carlo simulation of the Markov Chain is then used to estimate the posterior density. The theoretical background on Markov chains is provided and the way to build the transition matrix of the Markov Chain is illustrated with a simple, but realistic, model for data generation . Simulated data are used to illustrate the performance of the method and to show that it can easily cope with neurons generating spikes with highly dynamic waveforms and/or generating strongly overlapping clusters on Wilson plots.
Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs  [PDF]
Bernardo Kastrup
Computer Science , 1998,
Abstract: A high-level architecture of a Hybrid Reconfigurable CPU, based on a Philips-supported core processor, is introduced. It features the Philips XPLA2 CPLD as a reconfigurable functional unit. A compilation chain is presented, in which automatic implementation of time-critical program segments in custom hardware is performed. The entire process is transparent from the programmer's point of view. The hardware synthesis module of the chain, which translates segments of assembly code into a hardware netlist, is discussed in details. Application examples are also presented.
Reconfigurable design of neural networks hardware implementation
一种神经网络硬件实现的可重构设计

WAN Yong,WANG Qin,LI Zhan-cai,LI Ang,
万 勇
,王 沁,李占才,李 昂

计算机应用 , 2006,
Abstract: The BP networks was taken as an example and a reconfigurable method of neural networks(NN) hardware implementation was proposed.Based on this reconfigurable architecture and components,NN with different scales,transfer functions or learning algorithms could be implemented flexibly and fast.The implementation and test of a pattern recognition problem prove the feasibility of this method.
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