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Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory  [PDF]
Subashri T,Arunachalam R,Gokul Vinoth Kumar B,Vaidehi V
International Journal of VLSI Design & Communication Systems , 2010,
Abstract: A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
FPGA Based A New Low Power and Self-Timed AES 128-bit Encryption Algorithm for Encryption Audio Signal  [cached]
Bahram Rashidi,Bahman Rashidi
International Journal of Computer Network and Information Security , 2013,
Abstract: This paper presents, a low power 128-bit Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed architecture for encryption of audio signals. An asynchronous system is defined as one where the transfers of information between combinatorial blocks without a global clock signal. The self-timed architectures are asynchronous circuits which perform their function based on local synchronization signals called hand shake, independently from the other modules. This new architecture reduced spikes on current consumption and only parts with valid data are working, and also this design does not need any clock pulse. A combinational logic based Rijndael S-Box implementation for the Substitution Byte transformation in AES is proposed, its low area occupancy and high throughput therefore proposed digital design leads to reduction in power consumption. Mix-columns transformation is implemented only based on multiply-by-2 and multiply-by-3 modules with combinational logic. The proposed novel asynchronous self-timed AES algorithm is modeled and verified using FPGA and simulation results from encryption of sound signals is presented, until original characteristics are preserved anymore and have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. The achieved power consumption is 283 mW in clock frequency of 100 MHz.
FPGA Can Be Implemented By Using Advanced Encryption Standard Algorithm
P.AATHEESWARAN,DR. R.SURESH BABU
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering , 2013,
Abstract: This paper mainly focused in implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption.. This method can make it a very low-complex architecture, especially in saving the hardware resource in implementing the AES InverseSub Bytes module and Inverse Mix columns module. As the S -box is implemented by look-up-table in this design, the chip area and power can still be optimized. The new Mix Column transformation improves the performance of the inverse cipher and also reduces the complexity of the system that supports the inverse cipher. As a result this transformation has relatively low relevant diffusion power .This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
Parity Based Fault Detection Approach for the Low Power S-Box and Inverse S-Box  [PDF]
P.Jemima Anlet,, M.Jagadeeswari
International Journal of Computer Technology and Electronics Engineering , 2012,
Abstract: Advanced Encryption Standard (AES) has been made as the first choice for many critical applications because of the high level of security and the fast hardware and software implementations, many of which are power and resource constrained and requires reliable and efficient hardware implementations. In addition to the efficiency requirements of the AES, it must be reliable against transient and permanent internal faults or malicious faults aiming at revealing the secret key. In this paper, parity-based fault detection architecture of the S-box and the Inverse S-box for designing high performance fault detection structures of the AES is presented. The proposed parity-based fault detection approach is based on the low-cost composite field implementations of the S-box and the inverse S-box. Instead of using look-up tables for the S-box (Inverse S-box) and its parity prediction, logical gate implementations based on the composite field are utilized and hence the area gets reduced. This parity-based fault detection scheme reaches the maximum fault coverage when compared to other methods of fault detection. The proposed fault detection of the S-box and the inverse S-box in this paper have the least area and power consumption compared to their counterparts with similar fault detection capabilities
Enhanced Throughput AES Encryption
Kunal Lala,Ajay Kumar,Amit Kumar
International Journal of Electronics and Computer Science Engineering , 2012,
Abstract: This paper presents our experience in implementing the Advanced Encryption Standard (AES) algorithm. We have used 128 bit block size and 128 bit cipher key for the implementation. The AES also known as Rijndael algorithm is used to ensure security of transmission channels. Xilinx design tool 13.3 and Xilinx project navigator design tool are used for synthesis and simulation. Very high speed integrated circuit hardware description language (VHDL) is used for coding. The fully pipelined design was implemented on Virtex 6 FPGA family and a throughput of 49.3Gbits/s was achieved with an operational frequency of 384.793 MHz.
A Single Chip Design And Implementation Of AES -128/192/256 Encryption Algorithms  [PDF]
L.Thulasimani,,M.Madheswaran
International Journal of Engineering Science and Technology , 2010,
Abstract: In this paper an efficient hardware architecture design and implementation of all candidates of AES encryption standards AES-128, AES-192 and AES-256 on the same hardware is proposed. AES algorithm proposed by NIST has been widely accepted as best cryptosystem for wireless communication security. The hardware implementation is useful in wireless security like military and mobile phones. This contribution investigates implementation of AES Encryption with regards to FPGA and VHDL.Optimized and synthesized VHDL code for AES-128, AES-192 and AES-256 for encryption of 128-bit data is implemented. Xilinx ISE 9.2i software is used for simulation. Eachalgorithm is tested with sample vectors provided by NIST output results are perfect with minimal delay. The proposed design consumes less power and area which is suitable battery driven mobile phones. Throughput reaches the value of 666.67 Mbps for encryption of 128- bit data with AES-128 key with FPGA device XC2V6000BF957-6.
Using Cipher Key to Generate Dynamic S-Box in AES Cipher System  [PDF]
Razi Hosseinkhani,H. Haj Seyyed Javadi
International Journal of Computer Science and Security , 2012,
Abstract: The Advanced Encryption Standard (AES) is using in a large scale of applications that need toprotect their data and information. The S-Box component that used in AES is fixed, and notchangeable. If we can generate this S-Box dynamically, we increase the cryptographic strength ofAES cipher system. In this paper we intend to introduce new algorithm that generate S-Boxdynamically from cipher key. We describe how S-Box can be generated dynamically from cipherkey and finally analyze the results and experiments.
AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization
Samir El Adib,Naoufal Raissouni
International Journal of Information and Network Security (IJINS) , 2012, DOI: 10.11591/ijins.v1i2.530
Abstract: In the present paper we present an architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware. Rijndael algorithm is the new AES adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES). Compared to software implementation, hardware implementation of Rijndael algorithm provides more physical security as well as higher speed. The first factor to be considered on implementing AES is the application. High-speed designs are not always desired solutions. In some applications, such as mobile computing and wireless communications, smaller throughput is demanded. Architecture presented uses memory modules (i.e., Dual-Port RAMs) of Field-Programmable Gate Array (FPGAs) for storing all the results of the fixed operations (i.e., Look-Up Table), and Digital Clock Manager (DCM) that we used effectively to optimize the execution time, reduce design area and facilitates implementation in FPGA. The architecture consumes only 326 slices plus 3 Block Random Access Memory (BRAMs). The throughput obtained was of 270 Mbits/s. The target hardware used in this paper is Spartan XC3S500E FPGA from Xilinx. Results are presented and compared with other reference implementations, as known from the technical literature. The presented architecture can be used in a wide range of embedded applications.
Image Encryption and Decryption using AES  [PDF]
Manoj. B,Manjula N Harihar
International Journal of Engineering and Advanced Technology , 2012,
Abstract: In today’s world most of the communication is done using electronic media. Data Security is widely used to ensure security in communication, data storage and transmission. We have Advanced Encryption Standard (AES) which is accepted as a symmetric cryptography standard for transferring block of data securely. The available AES algorithm is used for text data and it is also suitable for image encryption and decryption to protect the confidential image data from an unauthorized access. This project proposes a method in which the image data is an input to AES Encryption to obtain the encrypted image, and the encrypted image is the input to AES Decryption to get the original image. In this paper, we implement the 128 bit AES for image encryption and decryption which is synthesized and simulated on FPGA family of Spartan-6 (XC6SLX25) using Xilinx ISE 12.4 tool in Very high speed integrated circuit Hardware Description Language (VHDL) and shall be verified with the help of its simulation result.
Acceleration of AES encryption on CUDA GPU  [cached]
Keisuke Iwai,Naoki Nishikawa,Takakazu Kurokawa
International Journal of Networking and Computing , 2012,
Abstract: GPU exhibits the capability for applications with a high level of parallelism despite its low cost. The support of integer and logical instructions by the latest generation of GPUs enables us to implement cipher algorithms more easily. However, decisions such as parallel processing granularity and memory allocation impose a heavy burden on programmers. Therefore, this paper presents results of several experiments that were conducted to elucidate the relation between memory allocation styles of variables of AES and granularity as the parallelism exploited from AES encoding processes using CUDA with an NVIDIA GeForce GTX285 (Nvidia Corp.). Results of these experiments showed that the 16 bytes/thread granularity had the highest performance. It achieved approximately 35 Gbps throughput. It also exhibited differences of memory allocation and granularity effects around 2%–30% for performance in standard implementation. It shows that the decision of granularity and memory allocation is the most important factor for effective processing in AES encryption on GPU. Moreover, implementation with overlapping between processing and data transfer yielded 22.5 Gbps throughput including the data transfer time.
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