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Validating Avionics Conceptual Architectures with Executable Specifications
Nils Fischer,Horst Salzwedel
Journal of Systemics, Cybernetics and Informatics , 2012,
Abstract: Current avionics systems specifications, developed after conceptual design, have a high degree of uncertainty. Since specifications are not sufficiently validated in the early development process and no executable specification exists at aircraft level, system designers cannot evaluate the impact of their design decisions at aircraft or aircraft application level. At the end of the development process of complex systems, e. g. aircraft, an average of about 65 per cent of all specifications have to be changed because they are incorrect, incomplete or too vaguely described. In this paper, a model-based design methodology together with a virtual test environment is described that makes complex high level system specifications executable and testable during the very early levels of system design. An aircraft communication system and its system context is developed to demonstrate the proposed early validation methodology. Executable specifications for early conceptual system architectures enable system designers to couple functions, architecture elements, resources and performance parameters, often called non-functional parameters. An integrated executable specification at Early Conceptual Architecture Level is developed and used to determine the impact of different system architecture decisions on system behavior and overall performance.
Quest-V: A Virtualized Multikernel for Safety-Critical Real-Time Systems  [PDF]
Richard West,Ye Li,Eric Missimer
Computer Science , 2013,
Abstract: Modern processors are increasingly featuring multiple cores, as well as support for hardware virtualization. While these processors are common in desktop and server-class computing, they are less prevalent in embedded and real-time systems. However, smartphones and tablet PCs are starting to feature multicore processors with hardware virtualization. If the trend continues, it is possible that future real-time systems will feature more sophisticated processor architectures. Future automotive or avionics systems, for example, could replace complex networks of uniprocessors with consolidated services on a smaller number of multicore processors. Likewise, virtualization could be used to isolate services and increase the availability of a system even when failures occur. This paper investigates whether advances in modern processor technologies offer new opportunities to rethink the design of real-time operating systems. We describe some of the design principles behind Quest-V, which is being used as an exploratory vehicle for real-time system design on multicore processors with hardware virtualization capabilities. While not all embedded systems should assume such features, a case can be made that more robust, safety-critical systems can be built to use hardware virtualization without incurring significant overheads.
Generic Hardware Architectures for Sampling and Resampling in Particle Filters  [cached]
Athalye Akshay,Boli? Miodrag,Hong Sangjin,Djuri? Petar M
EURASIP Journal on Advances in Signal Processing , 2005,
Abstract: Particle filtering is a statistical signal processing methodology that has recently gained popularity in solving several problems in signal processing and communications. Particle filters (PFs) have been shown to outperform traditional filters in important practical scenarios. However their computational complexity and lack of dedicated hardware for real-time processing have adversely affected their use in real-time applications. In this paper, we present generic architectures for the implementation of the most commonly used PF, namely, the sampling importance resampling filter (SIRF). These provide a generic framework for the hardware realization of the SIRF applied to any model. The proposed architectures significantly reduce the memory requirement of the filter in hardware as compared to a straightforward implementation based on the traditional algorithm. We propose two architectures each based on a different resampling mechanism. Further, modifications of these architectures for acceleration of resampling process are presented. We evaluate these schemes based on resource usage and latency. The platform used for the evaluations is the Xilinx Virtex II pro FPGA. The architectures presented here have led to the development of the first hardware (FPGA) prototype for the particle filter applied to the bearings-only tracking problem.
Unrolled Polar Decoders, Part I: Hardware Architectures  [PDF]
Pascal Giard,Gabi Sarkis,Claude Thibeault,Warren J. Gross
Computer Science , 2015,
Abstract: This is the first in a two-part series of papers on unrolled polar decoders. In this paper (Part I), we present a family of architectures for hardware polar decoders using a reduced-complexity successive-cancellation decoding algorithm. The resulting fully-unrolled architectures are capable of achieving a coded throughput in excess of 400 Gbps on an FPGA, two orders of magnitude greater than current state-of-the-art polar decoders. Moreover, the proposed architectures are flexible in a way that makes it possible to explore the trade-off between resource usage and throughput.
Hardware Architectures for the Orthogonal and Biorthogonal Wavelet Transform  [PDF]
G. Knowles
VLSI Design , 2002, DOI: 10.1080/1065514021000012110
Abstract: In this note, optimal hardware architectures for the orthogonal and biorthogonal wavelet transforms are presented. The approach used here is not the standard lifting method, but takes advantage of the symmetries inherent in the coefficients of the transforms and the decimation/interpolation operators. The design is based on a highly optimized datapath, which seamlessly integrates both orthogonal and biorthogonal transforms, data extension at the edges and the forward and inverse transforms. The datapath design could be further optimized for speed or low power. The datapath is controlled by a small fast control unit which is hard programmed according to the wavelet or wavelets required by the application.
Parallel Hardware Architectures for the Cryptographic Tate Pairing  [cached]
Guido M. Bertoni,Luca Breveglieri,Pasqualina Fragneto,Gerardo Pelosi
International Journal of Network Security , 2008,
Abstract: Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relevant research topic. Since such functions are very complex and slow in software, dedicated hardware (HW) implementations are worthy of being studied, but presently only very preliminary research is available. This work affords the problem of designing parallel dedicated HW architectures, i.e.,co-processors, for the Tate pairing, in the case of the Duursma-Lee algorithm in characteristic 3. Formal scheduling methodologies are applied to carry out an extensive exploration of the architectural solution space, evaluating the obtained structures by means of different figures of merit such as computation time, circuit area and combinations thereof. Comparisons with the (few) existing proposals are carried out, showing that a large space exists for the efficient parallel HW computation of pairings.
Hardware architectures for Successive Cancellation Decoding of Polar Codes  [PDF]
Camille Leroux,Ido Tal,Alexander Vardy,Warren J. Gross
Mathematics , 2010,
Abstract: The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancellation decoding. Motivated by the rapid progress in the theory of polar codes, we propose a family of architectures for efficient hardware implementation of successive cancellation decoders. We show that such decoders can be implemented with O(n) processing elements and O(n) memory elements, while providing constant throughput. We also propose a technique for overlapping the decoding of several consecutive codewords, thereby achieving a significant speed-up factor. We furthermore show that successive cancellation decoding can be implemented in the logarithmic domain, thereby eliminating the multiplication and division operations and greatly reducing the complexity of each processing element.
Performance analysis of massively parallel embedded hardware architectures for retinal image processing  [cached]
Nieto Alejandro,Brea Victor,Vilari?o David,Osorio Roberto
EURASIP Journal on Image and Video Processing , 2011,
Abstract: This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA).
A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation  [PDF]
Usha Bhanu.N,A.Chilambuchelvan
International Journal of VLSI Design & Communication Systems , 2012,
Abstract: Evaluating the previous work is an important part of developing new hardware efficient methods for theimplementation of DWT through Lifting schemes. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The architectures are represented in terms of parallel filter, row column, folded, flipping and recursive structures. The methods for scanning of images are the line-based and the block-based and their characteristics for the given application are given. The various architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes.
Multiplication of sparse Laurent polynomials and Poisson series on modern hardware architectures  [PDF]
Francesco Biscani
Computer Science , 2010,
Abstract: In this paper we present two algorithms for the multiplication of sparse Laurent polynomials and Poisson series (the latter being algebraic structures commonly arising in Celestial Mechanics from the application of perturbation theories). Both algorithms first employ the Kronecker substitution technique to reduce multivariate multiplication to univariate multiplication, and then use the schoolbook method to perform the univariate multiplication. The first algorithm, suitable for moderately-sparse multiplication, uses the exponents of the monomials resulting from the univariate multiplication as trivial hash values in a one dimensional lookup array of coefficients. The second algorithm, suitable for highly-sparse multiplication, uses a cache-optimised hash table which stores the coefficient-exponent pairs resulting from the multiplication using the exponents as keys. Both algorithms have been implemented with attention to modern computer hardware architectures. Particular care has been devoted to the efficient exploitation of contemporary memory hierarchies through cache-blocking techniques and cache-friendly term ordering. The first algorithm has been parallelised for shared-memory multicore architectures, whereas the second algorithm is in the process of being parallelised. We present benchmarks comparing our algorithms to the routines of other computer algebra systems, both in sequential and parallel mode.
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