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CMOS-compatible dense arrays of Ge quantum dots on the Si(001) surface: hut cluster nucleation, atomic structure and array life cycle during UHV MBE growth  [cached]
Arapkina Larisa,Yuryev Vladimir
Nanoscale Research Letters , 2011,
Abstract: We report a direct observation of Ge hut nucleation on Si(001) during UHV molecular beam epitaxy at 360°C. Nuclei of pyramids and wedges were observed on the wetting layer (WL) (M × N) patches starting from the coverage of 5.1 and found to have different structures. Atomic models of nuclei of both hut species have been built as well as models of the growing clusters. The growth of huts of each species has been demonstrated to follow generic scenarios. The formation of the second atomic layer of a wedge results in rearrangement of its first layer. Its ridge structure does not repeat the nucleus. A pyramid grows without phase transitions. A structure of its vertex copies the nucleus. Transitions between hut species turned out to be impossible. The wedges contain point defects in the upper corners of the triangular faces and have preferential growth directions along the ridges. The derived structure of the {105} facet follows the paired dimer model. Further growth of hut arrays results in domination of wedges, and the density of pyramids exponentially drops. The second generation of huts arises at coverages >10 ; new huts occupy the whole WL at coverages ~14 . Nanocrystalline Ge 2D layer begins forming at coverages >14 .
CMOS compatible dense arrays of Ge quantum dots on the Si(001) surface: Hut cluster nucleation, atomic structure, and array life cycle during UHV MBE growth  [PDF]
L. V. Arapkina,V. A. Yuryev
Physics , 2010, DOI: 10.1186/1556-276X-6-345
Abstract: We report a direct observation of Ge hut nucleation on Si(001) during UHV MBE. The study was carried out using a UHV instrument coupling MBE chamber and STM which enables the sample study on atomic level at any stage of treatment. Si wafers were deoxidized by annealing at 925C. Ge was deposited by electron beam evaporation; the coverage was varied from 3 to 14 \AA; the wafer temperature was 360C. The nuclei of pyramids and wedges were observed on the (MxN) wetting layer (WL) patches and found to have different structures. The atomic models of nuclei of both hut species have been built as well as the models of the growing clusters. The growth of huts of each species has been demonstrated to follow generic scenarios. The formation of the second atomic layer of the wedge results in rearrangement of its first layer. Its ridge structure does not repeat the nucleus. The pyramid grows without phase transitions. The structure of its vertex copies the nucleus. Transitions between hut species are impossible. The wedges contain point defects in the upper corners of the triangular faces and have preferential growth directions along the ridges. The derived structure of the {105} facet turned out to follow the PD model. Further growth of hut arrays results in domination of wedges, the density of pyramids exponentially drops. The heights of wedges are limited; no limitation of pyramid heights is observed. The second generation of huts arises at coverages >10 \AA; new huts occupy the whole WL.
CMOS-Compatible Nanowire Biosensors  [PDF]
Thanh C. Nguyen,Wanzhi Qiu,Matteo Altissimo,Paul G. Spizzirri,Laurens H. Willems van Beveren,Efstratios Skafidas
Physics , 2013,
Abstract: In this chapter, silicon nanowires that are compatible with CMOS fabrication processes have been described. It has been shown that these nanowires can be functionalized by conjugating monoclonal antibodies to their surface in order to build sensitive biochemical sensors. It has also been shown that by using frequency-based signals, all the necessary components to interrogate these nanowires can be built on low-cost CMOS processes.
Minimum energy path for the nucleation of misfit dislocations in Ge/Si(001) heteroepitaxy  [PDF]
Oleg Trushin,Emile Maras,Alexander Stukowski,Enzo Granato,See Chen Ying,Hannes Jonsson,Tapio Ala-Nissila
Physics , 2015,
Abstract: A mechanism for the formation of a 90{\deg} misfit dislocation at the Ge/Si(001) interface has been determined from atomic scale simulations based on the Stillinger-Weber interatomic potential function. A minimum energy path connecting the coherent epitaxial state to a final state with a 90{\deg} misfit dislocation was found using the nudged elastic band method with atomic structure generated using a repulsive bias activation procedure. The energy along the path exhibits a first maximum as a 60{\deg} dislocation nucleates. An intermediate minimum along the path corresponds to an extended 60{\deg} dislocation. A subsequent energy maximum then occurs as a second 60{\deg} dislocation nucleates in a complementary, mirror glide plane, simultaneously starting from the surface and from the first 60{\deg} dislocation. The activation energy of the nucleation of the second dislocation is 30% lower than that of the first one showing that the formation of the second 60{\deg} dislocation is aided by the presence of the first one. An understanding of the formation mechanism of 90{\deg} misfit dislocations could help design procedures for growing strain released Ge overlayers on Si(001) surfaces.
CMOS compatible athermal silicon microring resonators  [PDF]
Biswajeet Guha,Bernardo B. C. Kyotoku,Michal Lipson
Physics , 2009, DOI: 10.1364/OE.18.003487
Abstract: Silicon photonics promises to alleviate the bandwidth bottleneck of modern day computing systems. But silicon photonic devices have the fundamental problem of being highly sensitive to ambient temperature fluctuations due to the high thermo-optic (TO) coefficient of silicon. Most of the approaches proposed to date to overcome this problem either require significant power consumption or incorporate materials which are not CMOS-compatible. Here we demonstrate a new class of optical devices which are passively temperature compensated, based on tailoring the optical mode confinement in silicon waveguides. We demonstrate the operation of a silicon photonic resonator over very wide temperature range of greater than 80 degrees. The fundamental principle behind this work can be extended to other photonic structures such as modulators, routers, switches and filters.
Using dislocations to probe surface reconstruction in thick freely suspended liquid crystalline films  [PDF]
J. A. Collett,Daniel Martinez Zambrano
Physics , 2015, DOI: 10.1103/PhysRevE.92.040501
Abstract: Surface interactions can cause freely suspended thin liquid crystalline films to form phases different from the bulk material, but it is not known what happens at the surface of thick films. Edge dislocations can be used as a marker for the boundary between the bulk center and the reconstructed surface. We use noncontact mode atomic force microscopy to determine the depth of edge dislocations below the surface of freely suspended thick films of 4-n-heptyloxybenzylidene-4-n-heptylaniline (7O.7) in the crystalline B phase. 3.0 +/- 0.1 nm high steps are found with a width that varies with temperature between 56 C and 59 C. Using a strain model for the profile of liquid crystalline layers above an edge dislocation to estimate the depth of the dislocation, we find that the number of reconstructed surface layers increases from 4 to 50 layers as the temperature decreases from 59 C to 56 C. This trend tracks the behavior of the phase boundary in the thickness dependent phase diagram of freely suspended films of 7O.7, suggesting that the surface may be reconstructed into a smectic F region.
Ab initio Study of Misfit Dislocations at the SiC/Si(001) Interface  [PDF]
Giancarlo Cicero,Laurent Pizzagalli,Alessandra Catellani
Physics , 2007, DOI: 10.1103/PhysRevLett.89.156101
Abstract: The high lattice mismatched SiC/Si(001) interface was investigated by means of combined classical and ab initio molecular dynamics. Among the several configurations analyzed, a dislocation network pinned at the interface was found to be the most efficient mechanism for strain relief. A detailed description of the dislocation core is given, and the related electronic properties are discussed for the most stable geometry: we found interface states localized in the gap that may be a source of failure of electronic devices.
Catalyst preparation for CMOS-compatible silicon nanowire synthesis  [PDF]
Vincent T. Renard,M. Jublot,P. Gergaud,P. Cherns,D. Rouchon,A. Chabli,V. Jousseaume
Physics , 2010, DOI: 10.1038/nnano.2009.234
Abstract: Metallic contamination was key to the discovery of semiconductor nanowires, but today it stands in the way of their adoption by the semiconductor industry. This is because many of the metallic catalysts required for nanowire growth are not compatible with standard CMOS (complementary metal oxide semiconductor) fabrication processes. Nanowire synthesis with those metals which are CMOS compatible, such as aluminium and copper, necessitate temperatures higher than 450 C, which is the maximum temperature allowed in CMOS processing. Here, we demonstrate that the synthesis temperature of silicon nanowires using copper based catalysts is limited by catalyst preparation. We show that the appropriate catalyst can be produced by chemical means at temperatures as low as 400 C. This is achieved by oxidizing the catalyst precursor, contradicting the accepted wisdom that oxygen prevents metal-catalyzed nanowire growth. By simultaneously solving material compatibility and temperature issues, this catalyst synthesis could represent an important step towards real-world applications of semiconductor nanowires.
CMOS-compatible graphene photodetector covering all optical communication bands  [PDF]
Andreas Pospischil,Markus Humer,Marco M. Furchi,Dominic Bachmann,Romain Guider,Thomas Fromherz,Thomas Mueller
Physics , 2013, DOI: 10.1038/NPHOTON.2013.240
Abstract: Optical interconnects are becoming attractive alternatives to electrical wiring in intra- and inter-chip communication links. Particularly, the integration with silicon complementary metal-oxide-semiconductor (CMOS) technology has received considerable interest due to the ability of cost-effective integration of electronics and optics on a single chip. While silicon enables the realization of optical waveguides and passive components, the integration of another, optically absorbing, material is required for photodetection. Germanium or compound semiconductors are traditionally used for this purpose; their integration with silicon technology, however, faces major challenges. Recently, graphene has emerged as a viable alternative for optoelectronic applications, including photodetection. Here, we demonstrate an ultra-wideband CMOS-compatible photodetector based on graphene. We achieve multi-gigahertz operation over all fiber-optic telecommunication bands, beyond the wavelength range of strained germanium photodetectors, whose responsivity is limited by their bandgap. Our work complements the recent demonstration of a CMOS-integrated graphene electro-optical modulator, paving the way for carbon-based optical interconnects.
The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process  [cached]
Jang Moongyu,Park Youngsam,Jun Myungsim,Hyun Younghoon
Nanoscale Research Letters , 2010,
Abstract: Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and 94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.
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