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Reducing test-data volume and test-power simultaneously in LFSR reseeding-based compression environment

Wang Weizheng,Kuang Jishun,You Zhiqiang,Liu Peng,

半导体学报 , 2011,
Abstract: 集成电路测试中过高的测试功耗和日益增长的测试数据量是半导体工业面临的两大问题。本文提出了一种在基于线性反馈移位寄存器重播种的压缩环境下基于扫描块的测试向量编码方案。同时,本文也介绍了一种新颖的扫描块重聚类算法。本文的主要贡献是给出了一种灵活的测试应用框架,它能够极大地减少扫描移位期间的跳变个数和经由LFSR重播种生成的确定位的数目。因此,文中方案能够极大地降低测试功耗和测试数据量。在ISCAS’89基准电路上使用Mintest测试集进行的实验表明,本文方法能够减少72%-94%的跳变,并且能获得高达74%-94%的测试压缩率。
Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern  [cached]
S. Saravanan,Har Narayan Upadhyay
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: Aim of this study is to focus on reducing test pattern with effective Linear Feedback Shift Register (LFSR) reseeding. Test data volume of modern devices for testing increases rapidly corresponding to the size and complexity of the Systems-on-Chip (SoC). LFSR is a good pseudorandom pattern generator, which generates all possible test vectors with the help of the tap sequence. It can achieve high fault coverage by reducing correlation between the test vectors. Reseeding is a powerful method for reducing the test data volume and storage. This study presents a new LFSR reseeding technique for efficient reduction of test pattern. A new encoding technique is proposed in this study which is used to reduce the size of the test data. Size of the test data can be reduced by LFSR clock which is inactive for several clock cycles after the input seed is given. When the clock goes to inactive state, a rotate right shift operation is done on the seed to get all the remaining possible values. After getting all the possible values for that seed a new seed is given by making the clock active. Test data volume is reduced by storing the data only when the clock is active. With in the reduced clocks, rest of all the remaining test vectors was derived. A special Control logic is used to make the clock active as well as inactive. Experimental results are targeted to ISCAS89 benchmark circuits.
The LFSR and BCA VHDL Models for Built-in Self-test Circuits
J. Mitrych
Radioengineering , 2002,
Abstract: The various test structures are proposed for BIST techniques [1],[2]. A typical structure used for generation of pseudo-random test setsis the linear feedback shift register (LFSR). The BIST techniques havewide application in testing whole devices and embedded components. Wefocus on the analysis of the state coverage, fault coverage, andoptimal structure of BIST schemes.
Analysis, Design, and Test of CDMA LFSR with Offset Mask Using Standard ICs  [PDF]
Mouhamed Fadel Diagana, Serigne Bira Gueye
Engineering (ENG) , 2016, DOI: 10.4236/eng.2016.84019
Abstract: Hardware implementation of Linear Feedback Shift Register (LFSR) plays a great and very important role in communication systems, and in many security devices. In this paper, a design of LFSR with offset mask has been presented, for Direct Sequence Code Division Multiple Access (DS-CDMA) applications. Integrated electronic components have been used. An accessible model facilitating the synthesis on Printed Circuit Boards (PCB) and implementation on Field Programmable Gate Array (FPGA) is offered. In addition, a temporal and spectral analysis of the circuit is performed in order to validate the design. This latter facilitates the generation of pseudo-random codes based on LFSR and their integration into electronic systems.
An Incremental Reseeding Strategy for Clustering  [PDF]
Xavier Bresson,Huiyi Hu,Thomas Laurent,Arthur Szlam,James von Brecht
Computer Science , 2014,
Abstract: In this work we propose a simple and easily parallelizable algorithm for multiway graph partitioning. The algorithm alternates between three basic components: diffusing seed vertices over the graph, thresholding the diffused seeds, and then randomly reseeding the thresholded clusters. We demonstrate experimentally that the proper combination of these ingredients leads to an algorithm that achieves state-of-the-art performance in terms of cluster purity on standard benchmarks datasets. Moreover, the algorithm runs an order of magnitude faster than the other algorithms that achieve comparable results in terms of accuracy. We also describe a coarsen, cluster and refine approach similar to GRACLUS and METIS that removes an additional order of magnitude from the runtime of our algorithm while still maintaining competitive accuracy.
A New Test Data Compression Scheme  [cached]
Ling Zhang,Jishun Kuang
Journal of Computers , 2011, DOI: 10.4304/jcp.6.7.1297-1301
Abstract: With the improvement of technology, more cores are placed on a single chip to form a system. The volumes of test data becomes a challenges for circuits test. The paper presents a test data compression which uses hybrid prefix code and a new test set regenerating algorithm. In essence, the technique uses two formats of prefix to encode for the new regenerated test set, and the regenerated test set is better suitable to our compression scheme. So it gain better compression ratio. Experimental results show that the proposed compression solution could re duce test data volume effectively with a simple decoding architecture.
VHDL Models with Usage of the LFSR_PCKG Package
J. Kovalsky,K. Vlcek,J. Mitrych
Radioengineering , 2002,
Abstract: LFSRs (Linear Feedback Shift Registers) are very often used in theBIST (Built-In Self-Test) methodology. Implementation of the LFSRs tothe design or application of digital system, which supports BISTtechniques or which only uses these LFSRs, can be done by VHDLlanguage. This paper presents VHDL models of the devices andsubroutines (e.g. test pattern generators, signature analysers). Modelsare based on LFSR structures with usage of the LFSR_PCKG packagedescribed in the (Kovalsky and Vlcek, 2001), which can be usedin the applications supporting BIST techniques. Devices are describedas behavioural and structural models. These models and descriptions canbe used e.g. in the (Kovalsky, 2001). The LFSR_PCKG was modifiedand new approach is presented. Naturally, there are presented somesynthesis conclusions of the VHDL models and applications in thispaper.
An Efficient Test Data Compression Technique Based on Codes
Fang Jianping,Hao Yue,Liu Hongxia,Li Kang,
Fang Jianping
,Hao Yue,Liu Hongxi,Li Kang

半导体学报 , 2005,
Abstract: This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes.The method makes a full analysis of the factors which influence test parameters:compression ratio,test application time,and area overhead.To improve the compression ratio,the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step.With a novel on-chip decoder,low test application time and low area overhead are obtained by hybrid run length codes.Finally,an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.
Enhanced Test Data Compression of Conflict Bit Using Clustering Technique  [cached]
S. Saravanan,Har Narayan Upadhyay
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: The aim of this study is to implement enhanced test data compression of conflict bit using clustering technique. Huge test patterns, larger power consumption and more accessing time are the various challenges encountered by present System on Chip (SOC) design. Various compression techniques have been developed to minimize the huge test patterns by reducing the size of the data which saves space and transmission time. Test quality of the test pattern can be improved by test data compression. By finding the proper conflict bit (‘U’) the proposed algorithm generates test patterns having high reduction in test compression. Small numbers of test patterns are generated using clustering technique. With proper test pattern clustering it is possible to achieve high level of compression. Validation of the proposed method is found by experimental results on ISCAS’89 and shows that compression ratio is achieved by 79% with less conflict test pattern.
Evolutionary Optimization in Code-Based Test Compression  [PDF]
Ilia Polian,Alejandro Czutro,Bernd Becker
Computer Science , 2007,
Abstract: We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In contrast to existing code-based methods, we allow unspecified values in matching vectors, which allows encoding of arbitrary test sets using a relatively small number of code-words. Experimental results for both stuck-at and path delay fault test sets for ISCAS circuits demonstrate an improvement compared to existing techniques.
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