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Low-voltage MOS Current Mode Logic for Low-Power and High Speed Applications  [PDF]
Yangbo Wu,Jianping Hu
Information Technology Journal , 2011,
Abstract: Low power design has already become the main challenge in the modern VLSI design community. The voltage scaling techniques have proved one of the most effective methods for low power design. In this study, the design method of the low-voltage low-power MOS Current-Mode Logic (MCML) in nanometer CMOS technology is addressed. The analytical formulation of minimum supply voltage of the two-level MCML is derived. The results show that the power consumption in MCML can be decreased by reducing the supply voltage VDD without degrading the performance of MCML. As examples, the low-voltage MCML 1-bit full adder and 4-2 compressor are designed and simulated by HSPICE at the 45 nm CMOS process using the NCSU PTM model. The simulation results show that the proposed 1-bit full adder can obtained about 36 and 31% energy savings compared with the conventional MCML and CMOS ones using normal supply voltage at 4.0 GHz, respectively. The low-voltage MCML 4-2 compressor based on full adders can obtained about 33% energy savings compared with the conventional CMOS one at 5.0 GHz.
MOS Current Mode Logic with Capacitive Coupling  [PDF]
Kirti Gupta,Neeta Pandey,Maneesha Gupta
ISRN Electronics , 2012, DOI: 10.5402/2012/473257
Abstract: A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18?μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application. 1. Introduction The rapid advances in the VLSI technology have led to the development of high-resolution mixed-signal applications. These applications demand high performance digital circuits to be integrated with analog circuitry on the same chip. MOS current mode logic (MCML) style has been widely used in digital circuits design for mixed-signal applications as they provide an analog friendly environment due to the low switching noise [1–4]. MCML circuits exhibit high switching speed, high noise immunity and better power efficiency at high operating frequencies along with a drawback of static power consumption [5–8]. In mixed-signal applications, the digital circuits are extensively used in the realization of digital signal processor functional units such as finite impulse response (FIR) filter and FFT module. The functional units are required to perform computations at high speed to efficiently use the bandwidth in communication systems which is also increasing. Therefore it is necessary to improve the speed of conventional MCML circuits. In this paper, a new MCML style with capacitive coupling that increases the switching speed of the circuits is proposed. The paper first presents a brief introduction to conventional MCML style in Section 2. Thereafter, the architecture of the MCML style with capacitive coupling is proposed in Section 3. The mechanism of capacitive coupling is explained, and an expression for the delay is derived. The theoretical propositions are validated through SPICE simulations using TSMC 0.18?μm CMOS technology parameters in Section 4. The simulation results of several logic gates and an asynchronous FIFO are also presented in the same section. Finally, the conclusions are drawn in Section 5. 2. Conventional MCML Circuits A conventional MCML circuit
Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits  [PDF]
Kirti Gupta,Neeta Pandey,Maneesha Gupta
ISRN Electronics , 2012, DOI: 10.5402/2012/529194
Abstract: Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18?μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented. 1. Introduction Digital VLSI circuits can be broadly classified into synchronous and asynchronous circuits. A synchronous circuit employs a common clock signal to provide synchronization between all the circuit components. The synchronous circuits suffer from the problems of clock distribution and clock skew which becomes a challenge to overcome as the technology scales down. Asynchronous circuits, on the other hand, are attractive replacements to synchronous designs as they perform synchronization through handshaking between their components. Some other advantages of asynchronous circuits include high speed, low power consumption, modular design, immunity to metastable behavior, and low susceptibility to electromagnetic interference [1]. Traditionally, the asynchronous circuits were implemented by using CMOS logic style but due to the substantial dynamic power consumption at high frequencies, CMOS logic style is usually not preferred. MOS Current Mode Logic (MCML) is found to be an alternative to the CMOS asynchronous circuits in the literature [2–5]. A conventional MCML circuit consists of a differential pull-down network (PDN), a current source, and a load. The PDN implements the logic function, the current source generates the bias current , while the load performs the current to voltage conversion [6]. The circuit has static power consumption given as the product of the supply voltage and the bias current. The power consumption can be lowered by either reducing the bias current or the supply voltage. The reduction in bias current is generally not favored as it degrades the speed [7]. Therefore, lowering the supply voltage of the circuit is preferred. One of the techniques suggested in [8, 9] is multithreshold MOS Current Mode Logic (MT-MCML) which uses multithreshold transistors in conventional MCML circuits. In this paper, MT-MCML technique has been applied to implement
Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits  [cached]
Ruiping Cao,Jianping Hu
Research Journal of Applied Sciences, Engineering and Technology , 2013,
Abstract: Scaling supply voltage is an efficient technique to achieve low power-delay product. This study presents low-power Single-Rail MOS Current Mode Logic (SRMCML) circuits which operate on near-threshold region. The near-threshold operations for the basic SRMCML circuits such as inverter/buffer, OR2/NOR2 and 2/NAND2, OR3/NOR3 and XOR3/NXOR3 are investigated. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process by varying supply voltage from 0.6V to 1.3V with 0.1V steps. Based on the simulation results, lowering supply voltage is advantageous. The power dissipations of the proposed near-threshold SRMCML basic gates are almost the same as the conventional Dual-Rail MCML (DRMCML) circuits and the delay of the SRMCML is less than the DRMCML because of its single-rail scheme.
Voltage Mode OTRA MOS-C Single Input Multi Output Biquadratic Universal Filter  [cached]
Rajeshwari Pandey,Neeta Pandey,Sajal Kumar Paul,Ajay Singh
Advances in Electrical and Electronic Engineering , 2012,
Abstract: In this paper, an Operational transresistance amplifier (OTRA) based MOS-C voltage mode single input multi output (SIMO) biquadratic universal filter configuration is proposed. The configuration is made fully integrated by implementing the resistors using matched transistors operating in the linear region. It exhibits the feature of orthogonal controllability of angular frequency and quality factor through gate bias voltage. The non-ideality analysis of the circuit is also given. Workability of the universal filter is demonstrated through PSPICE simulations using 0,5 μm CMOS process parameters provided by MOSIS (AGILENT).
Richa Singh,Rajesh Mehra
International Journal of Advances in Engineering and Technology , 2013,
Abstract: This paper provides low power solutions for Very Large Scale Integration design. The dynamic power consumption of CMOS circuits is rapidly becoming a major concern in VLSI design. By adiabatic technique dynamic power consumption in pull up network can be reduced and energy stored on the load capacitance can be recycled. In this paper different logic style multiplexes have been analyzed and low power 2:1 multiplexer is designed using positive feedback adiabatic logic. It has been observed that adiabatic multiplexer consumes 53.1% less power than energy economized pass-transistor (EEPL) multiplexer. An adiabatic compressor has been designed using PFAL logic, which has shown 79% improvement than conventional CMOS compressor in terms of power. All the simulations are carried out by Microwind 3.1 tool.
Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates  [PDF]
Muhammad Taher Abuelma'atti
Active and Passive Electronic Components , 2003, DOI: 10.1080/0882751031000073832
Abstract: In this letter a new technique is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. Since no transistors are working in saturation, the problem of fan-out is alleviated. To illustrate the proposed technique, a circuit for simultaneous realization of the logic functions NOT, OR, NAND and XOR is considered. SPICE simulation results, obtained with 3 V supply, are included
MCML D-Latch Using Triple-Tail Cells: Analysis and Design  [PDF]
Kirti Gupta,Neeta Pandey,Maneesha Gupta
Active and Passive Electronic Components , 2013, DOI: 10.1155/2013/217674
Abstract: A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18?μm CMOS technology parameters. 1. Introduction The advances in semiconductor technology have led to the integration of high performance digital and analog circuits on the same silicon substrate. The traditional CMOS logic style does not provide an analog friendly environment due to the large switching noise [1–3]. Many alternate logic styles have been suggested in [3–6] and the reference mentioned therein. MOS current mode logic (MCML) style is the most promising one due to the lower switching noise in comparison to traditional CMOS logic style [6–9]. Also, it exhibits better power delay than the traditional CMOS logic style at high frequencies [6–15]. Therefore, MCML style is appropriate for designing high performance digital circuits wherein a D-latch is widely used as a building block in different applications such as prescalars, frequency dividers, and sequential logic circuits [16–20]. The D-latch topology given in [16–20] is referred to as traditional D-latch and is based on the series-gating approach (i.e., stacked source-coupled transistor pairs) [9] which puts a limit on the minimum power supply. The power supply may, however, be lowered by reducing the number of stacked transistor pair levels with triple-tail cell concept [21–23]. In this paper, a new low-voltage MCML D-latch is proposed. The static parameters for the proposed D-latch are analytically modeled and applied to develop a design approach. From the knowledge of the transistor sizes, the delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage multiplexer is analyzed for high-speed and power-efficient design cases. A comparison in performance of the proposed D-latch with the traditional one is carried out for all the cases. The paper first briefs the
High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic  [PDF]
Shen-Fu Hsiao,Jia-Siang Yeh,Da-Yen Chen
VLSI Design , 2002, DOI: 10.1080/1065514021000054736
Abstract: An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.
Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI
M.Padmaja, V.N.V. Satya Prakash
International Journal of Computer Trends and Technology , 2012,
Abstract: The Low power and low energy has become an important issue in today’s consumer electronics. Any combinational circuit can be represented as a multiple inputs with single output. Multiplexers are used to design any digital combinational logic circuit. Hence it is required to design a multiplexer with low power consumption and high speed. The main objective of this paper is to design the multiplexer using complementary metal oxide semiconductor (CMOS) logic and pass-transistor logic styles.The power consumption, delay, area, transistor count of various logic styles are compared. This paper shows that static NMOS logic multiplexer is an optimum device level design which has characteristics of high speed with minimum power compared with other realizations. These different logic styles are compared by performing detailed transistor level simulations using CAD tools of DSCH3 and Micro wind 3.1 in submicron regime.
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