Abstract:
A large portion of the on chip power is consumed by the clock system which is made of the clockdistribution network and flip-flops. So the objective is to reduce the power consumption. Most of the on chippower is consumed by the clock system which is made of the clock distribution network and flip-flops. The“Conditional Data Mapping Flip Flop” (CDMFF) and “Clocked Pair Shared Implicit Pulsed Flip Flop”(CPSFF) are triggered using single edge of clock. In CPSFF, reducing capacity of the clock load byminimizing number of clocked transistor was elaborated. The drawbacks of single edge clocking system arehigh transistor count and floating node problem in critical path. Moreover it cannot be used in noiseintensive environment. The CDMFF and CPSFF are triggered using single edge clocking system. Here, thedesign of a Dual triggered CMOS circuit is proposed. The objective is to reduce the number of clockedtransistors and switching activities, thereby reducing the power dissipation. The proposed design isimplemented in Microwind 3.1 and simulated using DSCH. The frequency of the Dual triggered CMOScircuit is only half of the clock frequency of the single edge triggered CMOS circuit. Simulation analysisshows that the Dual triggered CMOS circuit reduces switching activities by about 40%, thus reducingdynamic power dissipation. Hence it is suitable for using in high performance and low power environments.

Abstract:
In Very Large Scale Integrated Circuits (VLSI) design, the existing Design-for-Test(DFT) based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR) for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

Abstract:
Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit testing models. In this paper, we present a multi-level graph partitioning algorithm for circuit partitioning, which will minimize the number of test vectors during a low power test in VLSI circuits. By reducing the number of test vectors, we can reduce the energy consumption during the test. Our experimental results with ISCAS bench mark circuits have shown that the power can be reduced up to 55%.

Abstract:
Reversible circuits for SR flip flop, JK flip flop, D flip flop, T flip flop, Master Slave D flip flop and Master Slave JK flip flop have been provided with three different logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier proposals for the same. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of New gates is an \textcolor{black}{artifact} and if it is allowed then every circuit block (unless there is a measurement) can be reduced to a single gate. Further, it is shown that a reversible flip flop can be constructed even without a feedback. In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have also been addressed.

Abstract:
This paper studies sequential methods for recovery of sparse signals in high dimensions. When compared to fixed sample size procedures, in the sparse setting, sequential methods can result in a large reduction in the number of samples needed for reliable signal support recovery. Starting with a lower bound, we show any coordinate-wise sequential sampling procedure fails in the high dimensional limit provided the average number of measurements per dimension is less then log s/D(P_0||P_1) where s is the level of sparsity and D(P_0||P_1) the Kullback-Leibler divergence between the underlying distributions. A series of Sequential Probability Ratio Tests (SPRT) which require complete knowledge of the underlying distributions is shown to achieve this bound. Motivated by real world experiments and recent work in adaptive sensing, we introduce a simple procedure termed Sequential Thresholding which can be implemented when the underlying testing problem satisfies a monotone likelihood ratio assumption. Sequential Thresholding guarantees exact support recovery provided the average number of measurements per dimension grows faster than log s/ D(P_0||P_1), achieving the lower bound. For comparison, we show any non-sequential procedure fails provided the number of measurements grows at a rate less than log n/D(P_1||P_0), where n is the total dimension of the problem.

Abstract:
A multiple phase partial scan design method that breaks critical cycles using a combination of valid circuit state information and conflict analysis is proposed. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops being selected. When all critical cycles in the circuit are broken, our method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure conflict rather than reducing the sequential depth. The proposed method tries to eliminate the conflicts and uses a conflict-analysis-based testability measure conflict. Sufficient experimental results are presented to validate the method.

Abstract:
We consider the problem of quickly detecting a signal in a sensor network when the subset of sensors in which signal may be present is completely unknown. We formulate this problem as a sequential hypothesis testing problem with a simple null (signal is absent everywhere) and a composite alternative (signal is present somewhere). We introduce a novel class of scalable sequential tests which, for any subset of affected sensors, minimize the expected sample size for a decision asymptotically, that is as the error probabilities go to 0. Moreover, we propose sequential tests that require minimal transmission activity from the sensors to the fusion center, while preserving this asymptotic optimality property.

Abstract:
Reversible logic has come to the forefront of theoretical and applied research today. Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. Latches and flip-flops are the most significant memory elements for the forthcoming sequential memory elements. In this paper, we proposed two new reversible logic gates MG-1 and MG-2. We then proposed new design techniques for latches and flip-flops with the help of the new proposed gates. The proposed designs are better than the existing ones in terms of number of gates, garbage outputs and delay.

Abstract:
Consider a decision maker who is responsible to dynamically collect observations so as to enhance his information about an underlying phenomena of interest in a speedy manner while accounting for the penalty of wrong declaration. Due to the sequential nature of the problem, the decision maker relies on his current information state to adaptively select the most ``informative'' sensing action among the available ones. In this paper, using results in dynamic programming, lower bounds for the optimal total cost are established. The lower bounds characterize the fundamental limits on the maximum achievable information acquisition rate and the optimal reliability. Moreover, upper bounds are obtained via an analysis of two heuristic policies for dynamic selection of actions. It is shown that the first proposed heuristic achieves asymptotic optimality, where the notion of asymptotic optimality, due to Chernoff, implies that the relative difference between the total cost achieved by the proposed policy and the optimal total cost approaches zero as the penalty of wrong declaration (hence the number of collected samples) increases. The second heuristic is shown to achieve asymptotic optimality only in a limited setting such as the problem of a noisy dynamic search. However, by considering the dependency on the number of hypotheses, under a technical condition, this second heuristic is shown to achieve a nonzero information acquisition rate, establishing a lower bound for the maximum achievable rate and error exponent. In the case of a noisy dynamic search with size-independent noise, the obtained nonzero rate and error exponent are shown to be maximum.

Abstract:
We propose a new approach to sequential testing which is an adaptive (on-line) extension of the (off-line) framework developed in [10]. It relies upon testing of pairs of hypotheses in the case where each hypothesis states that the vector of parameters underlying the dis- tribution of observations belongs to a convex set. The nearly optimal under appropriate conditions test is yielded by a solution to an efficiently solvable convex optimization prob- lem. The proposed methodology can be seen as a computationally friendly reformulation of the classical sequential testing.