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Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation  [cached]
Masaaki Iijima,Kayoko Seto,Masahiro Numa,Akira Tada
Journal of Computers , 2008, DOI: 10.4304/jcp.3.5.34-40
Abstract: Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of Vth variation on performance even at ultra low supply voltage less than 0.5 V.
Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration  [PDF]
Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Circuits and Systems (CS) , 2012, DOI: 10.4236/cs.2012.33034
Abstract: An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.
Line and Word Matching in Old Documents  [PDF]
A. Marcolino,Vitorino Ramos,Mario Ramalho,J. R. Caldas Pinto
Computer Science , 2004,
Abstract: This paper is concerned with the problem of establishing an index based on word matching. It is assumed that the book was digitised as better as possible and some pre-processing techniques were already applied as line orientation correction and some noise removal. However two main factor are responsible for being not possible to apply ordinary optical character recognition techniques (OCR): the presence of antique fonts and the degraded state of many characters due to unrecoverable original time degradation. In this paper we make a short introduction to word segmentation that involves finding the lines that characterise a word. After we discuss different approaches for word matching and how they can be combined to obtain an ordered list for candidate words for the matching. This discussion will be illustrated by examples.
Dual gate black phosphorus velocity modulated transistor  [PDF]
V. Tayari,N. Hemsworth,O. Cyr-Choinière,W. Dickerson,G. Gervais,T. Szkopek
Physics , 2015,
Abstract: The layered semiconductor black phosphorus has attracted attention as a 2D atomic crystal that can be prepared in ultra-thin layers for operation as field effect transistors. Despite the susceptibility of black phosphorus to photo-oxidation, improvements to the electronic quality of black phosphorus devices has culminated in the observation of the quantum Hall effect. In this work, we demonstrate the room temperature operation of a dual gated black phosphorus transistor operating as a velocity modulated transistor, whereby modification of hole density distribution within a black phosphorus quantum well leads to a two-fold modulation of hole mobility. Simultaneous modulation of Schottky barrier resistance leads to a four-fold modulation of transcon- ductance at a fixed hole density. Our work explicitly demonstrates the critical role of charge density distribution upon charge carrier transport within 2D atomic crystals.
A tunable, dual mode field-effect or single electron transistor  [PDF]
Beno?t Roche,Benoit Voisin,Xavier Jehl,Romain Wacquez,Marc Sanquer,Maud Vinet,Veeresh Deshpande,Bernard Previtali
Physics , 2012, DOI: 10.1063/1.3678042
Abstract: A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator channel.
Word-Representability of Line Graphs  [PDF]
Sergey Kitaev, Pavel Salimov, Christopher Severs, Henning Ulfarsson
Open Journal of Discrete Mathematics (OJDM) , 2011, DOI: 10.4236/ojdm.2011.12012
Abstract: A graph G=(V,E) is representable if there exists a word W over the alphabet V such that letters x and y alternate in W if and only if (x ,y) is in E for each x not equal to y . The motivation to study representable graphs came from algebra, but this subject is interesting from graph theoretical, computer science, and combinatorics on words points of view. In this paper, we prove that for n greater than 3, the line graph of an n-wheel is non-representable. This not only provides a new construction of non-repre- sentable graphs, but also answers an open question on representability of the line graph of the 5-wheel, the minimal non-representable graph. Moreover, we show that for n greater than 4, the line graph of the complete graph is also non-representable. We then use these facts to prove that given a graph G which is not a cycle, a path or a claw graph, the graph obtained by taking the line graph of G k-times is guaranteed to be non-representable for k greater than 3.
Miniaturized Dual-Band Matching Technique Based on Coupled-Line Transformer for Dual-Band Power Amplifiers Design
Shun Li;Bihua Tang;Yuanan Liu;Shulan Li;Cuiping Yu;Yongle Wu
PIER , 2012, DOI: 10.2528/PIER12072004
Abstract: This study presents a novel miniaturized dual-band coupled-line impedance transformer. This dual-band matching technique uses the characteristics of coupled-line and dual-band stubs to realize matching arbitrary complex impedance to arbitrary complex impedance at two arbitrary uncorrelated frequencies. Especially, it satisfies the demand of dual-band matching at two relatively closed operating frequencies (n= / ≤ 1.2), and occupy a very small circuit area with inherent DC-Block function. The proposed synthesis approach is validated by the design and fabrication of a 30 W gallium nitride (GaN)-based class-AB power amplifier (PA) for GSM and WCDMA at 1800 MHz and 2140 MHz. The PA's output matching network based on the proposed structure can accurately match 50 Ω to the ideal load impedances of the transistor at two designed frequency simultaneously and has 20% and 15% bandwidth for which the reflection coefficient magnitudes are less than 0.1, respectively.
Electrically Reconfigurable Dual Metal-Gate Planar Field-Effect Transistor for Dopant-free CMOS  [PDF]
Tillmann Krauss,Frank Wessely,Udo Schwalke
Physics , 2014,
Abstract: In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.
High Density Four Transistor SRAM Cell with low Power Consumption  [PDF]
Sushil Bhushan,Shishir Rastogi,Mayank Shastri,Asso. Professor Shyam Akashe
International Journal of Computer Technology and Applications , 2011,
Abstract: This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus power during read/write operation reduced. Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results obtained from this paper.
Investigation of the Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field Effect Transistor  [PDF]
Sneh Saurabh,M. Jagadesh Kumar
Physics , 2011, DOI: 10.1109/TED.2010.2093142
Abstract: In this paper, we propose the application of a Dual Material Gate (DMG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of DMG in a Strained Double Gate Tunnel Field Effect Transistor with a high-k gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics.
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