oalib
Search Results: 1 - 10 of 100 matches for " "
All listed articles are free for downloading (OA Articles)
Page 1 /100
Display every page Item
Low Power Reversible Parallel Binary Adder/Subtractor  [PDF]
H G Rangaraju,U. Venugopal,K N Muralidhara,K B Raja
Computer Science , 2010, DOI: 10.5121/vlsic.2010.1303
Abstract: In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Low Power Reversible Parallel Binary Adder/Subtractor  [PDF]
Rangaraju H G,Venugopal U,Muralidhara K N,Raja K B
International Journal of VLSI Design & Communication Systems , 2010,
Abstract: In recent years, Reversible Logic is becoming more and more prominent technology having its applications inLow Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays animportant role when energy efficient computations are considered. In this paper, Reversible eight-bit ParallelBinary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three designapproaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbageinput/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractorwith Design III is efficient compared to Design I, Design II and existing design
An Improved Structure Of Reversible Adder And Subtractor  [PDF]
Aakash Gupta,Pradeep Singla,Jitendra Gupta,Nitin Maheshwari
Computer Science , 2013,
Abstract: In today's world everyday a new technology which is faster, smaller and more complex than its predecessor is being developed. The increased number of transistors packed onto a chip of a conventional system results in increased power consumption that is why Reversible logic has drawn attention of Researchers due to its less heat dissipating characteristics. Reversible logic can be imposed over applications such as quantum computing, optical computing, quantum dot cellular automata, low power VLSI circuits, DNA computing. This paper presents the reversible combinational circuit of adder, subtractor and parity preserving subtractor. The suggested circuit in this paper are designed using Feynman, Double Feynman and MUX gates which are better than the existing one in literature in terms of Quantum cost, Garbage output and Total logical calculations.
On the Design and Analysis of Quaternary Serial and Parallel Adders  [PDF]
Anindya Das,Ifat Jahangir,Masud Hasan
Computer Science , 2010,
Abstract: Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.
Design of the Efficient Nanometric Reversible Subtractor Circuit  [cached]
Mozhgan Shiri,Majid Haghparast
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: Reversible logic has comprehensive applications in communications, quantum computing, low power VLSI design, computer graphics, cryptography, nanotechnology, and optical computing. It has received significant attention in low power dissipating circuit design in the past few years. While several researchers have inspected the design of reversible logic units, there is not much reported works on reversible subtractors. In this paper we proposed the quantum equivalent circuit for SRK gate and we have computed the quantum cost of SRK gate. We also showed that how SRK gate can work singly as a half-subtractor circuit. It is being tried to design the circuit optimal in terms of number of reversible gates, number of garbage outputs, number of constant inputs, and quantum cost with compared to the existing circuits. At last we proposed an implementation of the new full-subtractor circuit based on SRK gate. All the designs have nanometric scales.
A molecular half-adder and half-subtractor based on pyrylium
ChaoTun Cao,Hui Liu,Xiao-Qing Zhu,Jin-Pei Cheng
Chinese Science Bulletin , 2010, DOI: 10.1007/s11434-010-4050-2
Abstract: A very simple molecular cation, 4-(4-dimethylaminophenyl)-2,6-diphenylpyrylium, has been demonstrated to have a function of molecular half-adder and half-subtractor according to the detectable spectroscopic changes of the molecular system in response to the inputs of acid and base. Distinct algebraic operations can be performed in this reconfigurable molecular logic system.
Minimization of Reversible Adder Circuits
Saiful Islam,Rafiqul Islam
Asian Journal of Information Technology , 2012,
Abstract: Losing information causes losing power. Information is lost when the input vector cannot be uniquely recovered from the output vector of a combinational circuit. The input vector of reversible circuit can be uniquely recovered from the output vector. In this study we have emphasized on the design of reversible adder circuits that is efficient in terms of gate count, garbage outputs and quantum cost and that can be technologically mapped. It has been analyzed and demonstrated that the results of our proposed adder circuits shows better performance compared to similar type of existing designs. Technology independent equations required to evaluate these circuits have also been given.
A Novel Nanometric Fault Tolerant Reversible Subtractor Circuit  [cached]
Mozhgan Shiri,Majid Haghparast,Vahid Shahbazi
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: Reversibility plays an important role when energy efficient computations are considered. Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing and nanotechnology in the recent years. This study proposes a new fault tolerant reversible half-subtractor and a new fault tolerant reversible full-subtractor circuit with nanometric scales. Also in this paper we demonstrate how the well-known and important, PERES gate and TR gate can be synthesized from parity preserving reversible gates. All the designs have nanometric scales.
An Efficient Reversible Design of BCD Adder  [PDF]
T.S.R.Krishna Prasad,Y.Satyadev
International Journal of Computer Technology and Applications , 2012,
Abstract: Nowadays, Reversible logic plays animportant role in vlsi design. It has voluminousapplications in quantum computing, optical computing,quantum dot cellular automata and digital signalprocessing. Adders are key components in manycomputational units, so design efficient binary codeddecimal (BCD) adder using reversible gates is needed. Itis not possible to calculate quantum cost withoutimplementation of reversible logic. This paper proposea new design for BCD adder that optimized in terms ofquantum cost, memory usage and number of reversiblegates. The important reversible gates used for reversiblelogic synthesis are NOT gate, CNOT gate, Toffoli gate,peres gate, TR gate and MTSG gate
VHDL Implementation of Non Restoring Division Algorithm Using High Speed Adder/Subtractor
SUKHMEET KAUR, SUMAN, MANPREET SINGH MANNA, RAJEEV AGARWAL
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering , 2013,
Abstract: Binary division is basically a procedure to determine how many times the divisor D divides the dividend B thus resulting in the quotient Q. At each step in the process the divisor D either divides B into a group of bits or it does not. The divisor divides a group of bits when the divisor has a value less than or equal to the value of those bits. Therefore, the quotient is either 1 or 0. The division algorithm performs either an addition or subtraction based on the signs of the divisor and the partial remainder. There are number of binary division algorithm like Digit Recurrence Algorithm restoring, non-restoring and SRT Division (Sweeney, Robertson, and Tocher), Multiplicative Algorithm, Approximation Algorithms, CORDIC Algorithm and Continued Product Algorithm. This paper focus on the digit recurrence non restoring division algorithm, Non restoring division algorithm is designed using high speed subtractor and adder. High speed adder and subtractor are used to speed up the operation of division. Designing of this division algorithm is done by using VHDL and simulated using Xilinx ISE 8.1i software has been used and implemented on FPGA xc3s100e-5vq100.
Page 1 /100
Display every page Item


Home
Copyright © 2008-2017 Open Access Library. All rights reserved.