Search Results: 1 - 10 of 100 matches for " "
All listed articles are free for downloading (OA Articles)
Page 1 /100
Display every page Item
A Novel Low Power UWB Cascode SiGe BiCMOS LNA with Current Reuse and Zero-Pole Cancellation  [PDF]
Chunbao Ding,Wanrong Zhang,Dongyue Jin,Hongyun Xie,Pei Shen,Liang Chen
Computer Science , 2012,
Abstract: A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt-shunt feedback and resistance-capacitor (RC) series-series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35{\mu}m SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3~4.1dB, gain of 18.9~20.2dB, gain flatness of \pm0.65dB, input third order intercept point (IIP3) of -7dBm at 6GHz, exhibits less than 16ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consuming is only 18mW.
A High-Gain Cmos Lna for 2.4/5.2-GHz WLAN Applications
Sen Wang;Bo-Zong Huang
PIER C , 2011, DOI: 10.2528/PIERC11032705
Abstract: This paper describes a high-gain CMOS low-noise amplifier (LNA) for 2.4/5.2-GHz WLAN applications. The cascode LNA uses an inductor at the common-gate transistor to increase its transconductance equivalently, and therefore it enhances the gain effectively with no additional power consumption. The LNA is matched concurrently at the two frequency bands, and the input/output matching networks are designed with two notch frequencies to shape the frequency response. The dual-band LNA with the common-gate inductor is designed, implemented, and verified in a standard 0.18-μm CMOS process. The fabricated LNA which consumes 7.2 mW features gains of 14.2 dB and 14.6 dB, and noise figures of 4.4 dB and 3.7 dB at the 2.4-GHz and 5.2-GHz frequency bands, respectively. The proposed LNA demonstrates a 4.9-7.8 dB gain enhancement compared to conventional cascode LNAs, and the chip size is 1.06 mm × 0.79 mm including all testing pads.
Performance Evaluation of Different LNA’s having Noise Cancellation and Phase Linearity Characteristics for IR-UWB Systems.  [PDF]
Alpana P. Adsul,Shrikant K. Bodhe
International Journal of Engineering and Technology , 2011,
Abstract: In the UWB communication system receiver LNA is the essential module. In this paper two LNA architecture with noise cancellation and phase linearity are presented. The performance evaluation is carried out for low band UWB system having frequency range from 3 to 5 GHz and a wide band UWB system with frequency range from 3.1 to 10.6 GHz. The noise figure and the gain are major parameters considered while designing the LNA’s. This paper gives the detailed analysis for both low band as well as wide band LNA. The phase linear LNA achieves gain of 12 dB, a maximum noise figure of 2.6 dB for the wideband frequency range. Whereas, the noise cancellation low band LNA achieves a gain of 11.3 dB and the noise figure of 4.04 dB. The gain of wide band phase linear LNA is flat over the band of interest as compare to the noise cancellation LNA.
Low Noise Amplifier at 5.8GHz with Cascode and Cascaded Techniques Using T-Matching Network for Wireless Applications  [cached]
Abu Bakar Ibrahim,Abdul Rani Othman,Mohd Nor Husain,Mohammad Syahrir Johal
International Journal of Electrical and Computer Engineering , 2011, DOI: 10.11591/ijece.v1i1.63
Abstract: This project present a design of a 5.8 GHz low noise amplifier (LNA) design with cascode and cascaded techniques using T-matching network applicable for IEEE 802.16 standard. The amplifier use FHX76LP Low Noise SuperHEMT FET. The LNA designed used T-matching network consisting of lump element reactive element at the input and the output terminal. The cascode and cascaded low noise amplifier (LNA) produced gain of 36.8dB and noise figure (NF) at 1.3dB. The input reflection (S11) and output return loss (S22) are -11.4dB and -12.3dB respectively. The bandwidth of the amplifier is more than 1GHz. The input sensitivity is compliant with the IEEE 802.16 standards. Keyword: Cascode and Cascade LNA, Radio Frequency, T -Matching Network
ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic  [PDF]
Avireni Srinivasulu,Madugula Rajesh
Journal of Engineering , 2013, DOI: 10.1155/2013/595296
Abstract: Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180?nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation. 1. Introduction Differential logic was originally proposed as a logic style to eliminate static current and at the same time to provide a rail to rail swing on the output node. The cross coupling of pull-ups helps to speed-up transition. These circuits combine the concepts of differential circuits and positive feedback to provide high speed performance without the penalty of static power consumption. The key benefits of DCVSL are its low input capacitance, differential nature, and low power consumption. Heller et al. [1] proposed DCVSL that became popular due to its high speed performance over conventional static CMOS and the elimination of static current due to its cross coupled pull-up device connection. More recently, several new circuit styles based on the differential circuit concept have been proposed [2–5]. DCVSL circuit can outperform complex functions with a single differential tree network, minimizing the number of stages required and shorten the propagation delay when compared with conventional CMOS static gate designs. Enhanced Differential Cascode Voltage Switch Logic (EDCVSL) simplifies the logic tree of DCVSL and dramatically reduces the number of interconnections by eliminating the complementary inputs, while maintaining the features of DCVSL [6]. To increase the performance and reduce the power consumption, many clocked versions of the DCVSL gates have been introduced. The implementation of CMOS random logic with DCVSL has many advantages over the traditional static CMOS logic approach. First
A 12dB 0.7V W CMOS LNA for 866MHz UHF RFID Reader  [PDF]
Jie Li,S. M. Rezaul Hasan
Active and Passive Electronic Components , 2010, DOI: 10.1155/2010/702759
Abstract: The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866?MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this paper the finite ?? effect has been considered to improve the nanometric design, achieving simultaneous impedance and minimum noise matching at a very low power drain of 850? from a 0.7?V supply voltage. The LNA was fabricated using the IBM 130?nm CMOS process delivering a forward power gain ( ) of , a reverse isolation ( ) of , an output power reflection ( @866?MHz) of , and an input power reflection ( @866?MHz) of . It had a minimum pass-band of around 2.2?dB and a third-order input referred intercept point (IIP3) of . 1. Introduction RFID (radio-frequency identification) is one of the fastest growing wireless communication technologies for commercial product tracking. As the low noise amplifier (LNA) is the first block in the front-end of the RFID reader which is tuned at a certain transreceiver frequency, it needs to be designed optimally to minimize the noise for the following stages and avoid the distortion of the source signal (requires good linearity). To overcome design trade-off difficulties between gain, power, noise figure and matching in the optimization of the LNA, the design of the matching circuits at the input and the output are based, respectively, on minimal and maximal power transfer. In recent years, considerable research on CMOS LNA design in submicron technologies at 900?MHz have been reported by many authors in [1–4]. A lower frequency standard for UHF RFID at 866?MHz is also implemented in Europe, Africa, and New Zealand. Low power dissipation at low supply voltage is a significant design criterion for RFID applications synthesized by design trade-off between gain, , input and output impedance matching and high linearity. In this paper we discuss the design and the experimental results for a 0.7?V low-power 130?nm CMOS 866?MHz single-ended common-source telescopic cascode LNA using an power constrained simultaneous noise and impedance matching (PCSNIM [5, 6]) technique. 2. Principles and Circuit Design An inductively source degenerated telescopic cascode topology has been chosen for the 866?MHz RFID LNA design due to its current reuse structure and hence it consumes less bias current than the folded cascode. Figure 1 shows the circuit diagram of the proposed RFID LNA. and forms the cascode configuration and their bias currents are driven by and . , and form the output tank circuit tuned at 866?MHz with an angular frequency
Improvement of Transmit Data Bit Rate and Characteristic of Optical Modulator Driver Circuit by Cascode HBT

Shi Ruiying,Liu Xunchun,

半导体学报 , 2003,
Abstract: or:In generally,the transistor technology chosen must provide the cut-off frequency f T better than four times the bit rate of the network in order to achieve the required speeds and proper system margins.A novel cascode circuit reduces the cut-off frequency requirement to twice the bit rate.The reason why the transmit data bit rate of the cascode HBT circuit rises is analyzed.At the same time,the novel cascode circuit also provided an effective solution to the thermal runaway issue.
Low Power Folded Cascode OTA  [PDF]
Swati Kundra,Priyanka Soni,Anshul Kundra
International Journal of VLSI Design & Communication Systems , 2012,
Abstract: Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques havebeen developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and thesupply voltage 1.8V.
Hot carrier effects of SOI NMOS

Chen Jianjun,Chen Shuming,Liang Bin,Liu Biwei,Liu Zheng,Teng Zheqian,

半导体学报 , 2010,
Abstract: Hot carrier effect(HCE) is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation,a HCE degradation model for annular NMOS and two-edged NMOS is proposed.According to this model,we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate,and annular NMOS has more serious HCE degradation ...
A Cryogenic Ultra-Low-Noise MMIC-based LNA with a discrete First Stage Transistor Suitable for Radio Astronomy Applications  [PDF]
Mark A. McCulloch,Simon J. Melhuish,Lucio Piccirillo
Physics , 2013,
Abstract: In this paper a new design of MMIC based LNA is outlined. This design uses a discrete 100-nm InP HEMT placed in front of an existing InP MMIC LNA to lower the overall noise temperature of the LNA. This new approach known as the Transistor in front of MMIC (T+MMIC) LNA, possesses a gain in excess of 40dB and an average noise temperature of 9.4K compared to 14.5K for the equivalent MMIC-only LNA measured across a 27-33GHz bandwidth at a physical temperature of 8K. A simple ADS model offering further insights into the operation of the LNA is also presented and a potential radio astronomy application is discussed
Page 1 /100
Display every page Item

Copyright © 2008-2017 Open Access Library. All rights reserved.