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Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey  [PDF]
Usha S. Mehta,Kankar S. Dasgupta,Niranjan M. Devashrayee
VLSI Design , 2010, DOI: 10.1155/2010/670476
Abstract: The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for “don't care” bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s. 1. Introduction As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests, corresponding to data volume and test time, increases with each new fabrication process technology just to maintain test quality requirements. Conventional external testing involves storing all test vectors and test response on ATE. But these testers have limited speed, memory, and I/O channels. Testing cannot proceed any faster than the amount of time required to transfer the test data: ?Test time ≥ (amount of test data on tester)/(number of tester channels × tester clock rate) [1]. As a result, some companies are looking for compression well beyond 100X tester cycle reduction [2–4]. The paper is organized as follows. Section 2 describes the test data compression techniques and the qualities of a good technique. Section 3 presents existing run-length-based codes. Section 4 introduces the different methods of do not care bit filling for run-length-based code. Section 5 introduces entropy. Sections 6 and 7 present the experimental results of test data compression and test power with different methods of X filling. Section 8 compares the actual data compression for various methods claimed in literature with maximum possible compression predicted on the basis of entropy. Section 9 analyzes the nature of test data on the basis of various experimental results. Finally conclusions and future work
Test Data Compression Using Entry Derivative Mode of Dictionary

Liu Jie Yi Mao-xiang Zhu Yong,

电子与信息学报 , 2012,
Abstract: To lower cost of testing digital integrated circuits, compressing precomputed test set is an effective resolution way. A dictionary compression scheme using entry derivative and two-level coding is proposed based on digits of index far fewer than that of dictionary entry and enormous don’t-care bits in test data. The introduced cyclic shift operation can arbitrarily shift don’t-care bits in order without losing them so that derivative performances of entries are expanded and number of non-entry vectors is decreased. In addition, two-level regular coding is adopted to reduce volume of code words and complexity of decompression circuit. The experimental results show that the proposed scheme can farther heighten test data compression ratio and decrease test time.
Analysis of Test Data Compression Techniques Based on Complementary Huffman Coding
Kinjal A. Bhavsar,,Prof.Usha S.Mehta
International Journal of Engineering Science and Technology , 2011,
Abstract: In this paper we describe the complementary Huffman encoding technique for test data compression for SOC.In this method we use complementary correlations between two blocks which can reduce size of Huffman tree compare to full Huffman but higher compare to selective and optimal Huffman coding and also increase compression ratios compare to selective and Huffman coding methods. Test application timeis higher compare to full Huffman and less compare to selective and optimal selective Huffman coding.
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method  [PDF]
Usha Mehta,K. S. Dasgupta,N. M. Devashrayee
VLSI Design , 2011, DOI: 10.1155/2011/756561
Abstract: Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like “don't care bit filling” and “reordering” which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed “Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)” is a modification to earlier proposed “Hamming Distance based Reordering—Columnwise Bit Filling and Difference vector.” This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow. 1. Introduction The testing cost and testing power are the two well-known issues of current generation IC testing [1]. The test cost is directly related to test data volume and hence test data transfer time [2]. Test data compression can solve the problem of test cost by reducing the test data transfer time. The dynamic test power plays a major role in overall test power. The switching activity during test has a large contribution in dynamic power and hence in overall test power. The extensive use of IP cores in SoC has further exaggerated the testing problem. Because of the hidden structure of IP cores, the SoCs containing large IP cores can use only those test data compression techniques and switching reduction technique which do not require any modification or insertion in architecture of IP core. These methods should not also demand the use of ATPG, scan insertion, or any such testing tools. They should be capable to use ready-to-use test data coming with IP core for data compression and power reduction. This test data may be partially specified or fully
A New Test Data Compression Scheme  [cached]
Ling Zhang,Jishun Kuang
Journal of Computers , 2011, DOI: 10.4304/jcp.6.7.1297-1301
Abstract: With the improvement of technology, more cores are placed on a single chip to form a system. The volumes of test data becomes a challenges for circuits test. The paper presents a test data compression which uses hybrid prefix code and a new test set regenerating algorithm. In essence, the technique uses two formats of prefix to encode for the new regenerated test set, and the regenerated test set is better suitable to our compression scheme. So it gain better compression ratio. Experimental results show that the proposed compression solution could re duce test data volume effectively with a simple decoding architecture.
Cluster Based LFSR Reseeding for Test Data Compression  [cached]
S. Saravanan,K. Chakrapani,P. Selvakumar
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: Today’s System-on-Chip (SoC) represent high-complexity and it is moving towards the challenge of huge test patterns, more accessing time and larger power consumption. Test data compression is done to improve the test quality. This study presents a test pattern compression by the usage of suitable clustering technique and its corresponding decompression scheme. This scheme includes compression and decompression achieved by LFSR reseeding. Test data compression is widely used in the industry nowadays to reduce the amount of test data stored on the ATE and to decrease testing time. The proposed method requires no special ATPG. The proposed method is validated by the simulation and synthesis output.
An Efficient Test Data Compression Technique Based on Codes
Fang Jianping,Hao Yue,Liu Hongxia,Li Kang,
Fang Jianping
,Hao Yue,Liu Hongxi,Li Kang

半导体学报 , 2005,
Abstract: This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes.The method makes a full analysis of the factors which influence test parameters:compression ratio,test application time,and area overhead.To improve the compression ratio,the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step.With a novel on-chip decoder,low test application time and low area overhead are obtained by hybrid run length codes.Finally,an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.
Test Data Compression Scheme Based on Compatible Data Block Coding  [PDF]
Jin Shang,Liyong Zhang
Information Technology Journal , 2013,
Abstract: In order to reduce the storage requirements for the test pattern, a test data compression scheme based on compatible data block coding is presented. In the scheme, binary code is used to express the test data which are compatible or inversely compatible with reference data which are improved compression radio. The circuit structure of decompression with a Finite State Machine (FSM) and a Cyclical Scan Register (CSR) was proposed. Experimental results for the large ISCAS 89 benchmark circuits show that this scheme is a very efficient compression method than other compression schemes and the average compression ratio of up to 63.89%.
Low Power testing by don’t care bit filling technique
Chetan Sharma
International Journal of Computer Trends and Technology , 2011,
Abstract: Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing
Enhanced Test Data Compression of Conflict Bit Using Clustering Technique  [cached]
S. Saravanan,Har Narayan Upadhyay
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: The aim of this study is to implement enhanced test data compression of conflict bit using clustering technique. Huge test patterns, larger power consumption and more accessing time are the various challenges encountered by present System on Chip (SOC) design. Various compression techniques have been developed to minimize the huge test patterns by reducing the size of the data which saves space and transmission time. Test quality of the test pattern can be improved by test data compression. By finding the proper conflict bit (‘U’) the proposed algorithm generates test patterns having high reduction in test compression. Small numbers of test patterns are generated using clustering technique. With proper test pattern clustering it is possible to achieve high level of compression. Validation of the proposed method is found by experimental results on ISCAS’89 and shows that compression ratio is achieved by 79% with less conflict test pattern.
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