oalib
Search Results: 1 - 10 of 100 matches for " "
All listed articles are free for downloading (OA Articles)
Page 1 /100
Display every page Item
用快燃物提高固体推进剂燃速  [PDF]
郭万东?,王珂?,丁温霞?
推进技术 , 1998,
Abstract: 介绍了运用快燃物提高固体推进剂燃速的方法。在6.86mpa下,当添加快燃物acp的量为5%时,丁羟推进剂燃速由73mm/s提高到119mm/s;且快燃物acp对推进剂的安全性能没有明显不良影响。
仿棉共聚酯纤维的制备及其性能表征  [PDF]
吉鹏,刘红飞,王朝生,陈向玲,王华平
纺织学报 , 2015,
Abstract: 普通聚酯纤维吸湿性差,易产生静电现象,染色需要在高温高压条件下进行,为改善聚酯纤维的综合服用舒适性,在聚酯中引入聚乙二醇柔性链段、季戊四醇、二氧化钛经共聚制备得到多组分改性共聚酯。对纤维形态结构调控,制备得到截面十字异形仿棉纤维。对仿棉共聚酯纤维的吸湿、抗静电性及染色性进行了测试表征。结果表明共聚酯具有良好的成纤性、力学性能,制备出的短纤维在标准温湿度环境下的回潮率为0.93%,5次洗涤后的比电阻为4.23×108Ω.cm,对气态水分具有快吸速干的特点,可以实现常压沸染。
Nanowire Volatile RAM as an Alternative to SRAM  [PDF]
Mostafizur Rahman,Santosh Khasanvis,Csaba Andras Moritz
Computer Science , 2014,
Abstract: Maintaining benefits of CMOS technology scaling is becoming challenging due to increased manufacturing complexities and unwanted passive power dissipations. This is particularly challenging in SRAM, where manufacturing precision and leakage power control are critical issues. To alleviate some of these challenges a novel non-volatile memory alternative to SRAM was proposed called nanowire volatile RAM (NWRAM). Due to NWRAMs regular grid based layout and innovative circuit style, manufacturing complexity is reduced and at the same time considerable benefits are attained in terms of performance and leakage power reduction. In this paper, we elaborate more on NWRAM circuit aspects and manufacturability, and quantify benefits at 16nm technology node through simulation against state-of-the-art 6T-SRAM and gridded 8T-SRAM designs. Our results show the 10T-NWRAM to be 2x faster and 35x better in terms of leakage when compared to high performance gridded 8T-SRAM design.
DEEP SUB-MICRON SRAM DESIGN FOR DRV ANALYSIS AND LOW LEAKAGE
Sanjay Kr Singh,Sampath Kumar,Arti Noor,D. S. Chauhan
International Journal of Advances in Engineering and Technology , 2011,
Abstract: This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data lines. While designing the SRAM, techniques such as circuit partitioning, divide word line and low power layout methodologies are reviewed to minimize the power dissipation.
5-氨基四唑硝仿盐的理论计算  [PDF]
刘威,李玉川,李小童,杨雨璋,林秋汉,庞思平
含能材料 , 2013,
Abstract: 采用量子化学方法研究了5-氨基四唑硝仿盐的结构和性能,计算了5-氨基四唑硝仿盐的密度、生成热、爆速、爆压等,其预测密度为1.93g·cm-3,估算爆速和爆压分别为9.47km·s-1和38.82GPa,爆轰性能高于TNT,RDX和HMX。
Design of Low Power Sram Memory Using 8t Sram Cell  [PDF]
Nahid Rahman,,B. P. Singh
International Journal of Recent Technology and Engineering , 2013,
Abstract: Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As modern technology is spreading fast, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the problems in 6T SRAM cell, researchers have proposed different SRAM topologies such as 8T, 9T, 10T etc. bitcell design. These designs can improve the cell stability but suffer from bitline leakage noise. In this paper, an SRAM memory has been designed to overcome power consumption problem. It also improves the Cell stability by increasing the Read Static-Noise-Margin.
杜仲集约速生技术研究  [PDF]
谭承普
中国中药杂志 , 1993,
Abstract: <正>笔者发现自然生杜仲苗被风或机械折断主干后,下部即萌发新芽,长出新梢既快又直。继而对杜仲全截速生作过以下试验。
Optimization of Embedded SRAM for Low Power and Testing
嵌入式SRAM的低功耗优化及测试

WANG Jiang-an,ZHUANG Yi-qi,JIN Zhao,LI Di,
王江安
,庄奕琪,靳钊,李迪

计算机科学 , 2010,
Abstract: 为了降低SRAM的功耗,提出了一种优化的SRAM.对改变较快的输入端引入操作数隔离技术,对比较电路的多位数据进行总线数据分割;给较大的时钟网络增加门控时钟,引入多种电源控制模式并增加隔离逻辑;将SRAM64K×32分解为8个SRAM8K×32子块,由八选一逻辑通过各子块的片选信号相连,使得同时只有一个子块处于读写状态.将优化的SRAM64K×32应用到SOC中,并通过增加旁路逻辑来测试各部分功耗.该SOC经90nm CMOS工艺成功流片.测试结果表明,优化的SRAM64K×32 功耗降低了29.569%,面积仅增加了0.836%.
可用于SRAM PUF的密钥提取方案
Key Extraction Schemes for SRAM PUF
 [PDF]

张亮亮,张翌维,孙瑞一,周源,王新安
- , 2017, DOI: 10.13209/j.0479-8023.2017.059
Abstract: 摘要 为了利用PUF获得芯片唯一、随机的密钥, 详细分析可用于SRAM PUF的密钥提取方案, 包括采用级联纠错码的硬判决和软判决译码方案。利用芯片上的实际SRAM PUF响应和软件仿真, 验证两种方案的效果。结果表明, 对于SRAM PUF, 软判决方案更加可靠和高效。
Abstract To acquire unique and random keys for chips from PUF, key extraction schemes for SRAM PUF are introduced. These schemes include the hard-decision and soft-decision decoding ones involving concatenated errorcorrecting code. By the actual responses of SRAM PUF’s on chips and software simulation, the effect of above two schemes is verified. The result shows that, for SRAM PUF, the soft-decision scheme is more reliable and efficient.
Optimization and Application of SRAM in 90nm CMOS Technology
90nm CMOS工艺SRAM的优化及应用

Zhou Qingjun,Liu Hongxia,
周清军
,刘红侠

半导体学报 , 2008,
Abstract: 提出了一种优化的SRAM,它的功耗较低而且能够自我修复.为了提高每个晶圆上的SRAM成品率,给SRAM增加冗余逻辑和E-FUSE box从而构成SR SRAM.为了降低功耗,将电源开启/关闭状态及隔离逻辑引入SR SRAM从而构成LPSR SRAM.将优化的LPSR SRAM64K×32应用到SoC中,并对LPSR SRAM64K×32的测试方法进行了讨论.该SoC经90nm CMOS工艺成功流片,芯片面积为5.6mm×5.6mm,功耗为1997mW.测试结果表明:LPSR SRAM64K×32功耗降低了17.301%,每个晶圆上的LPSRSRAM64K×32成晶率提高了13.255%.
Page 1 /100
Display every page Item


Home
Copyright © 2008-2017 Open Access Library. All rights reserved.