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留凤关复理石  [PDF]
地质学报 , 1979,
Abstract: 留凤关复理石,系指东秦岭冒地槽早三迭世留凤关群的复理石建造。它位于宝成铁路的凤县至聂家湾一带(图1),向西延至西秦岭。留凤关群,早有人认为属复理石沉积,不过都未提出具体资料。1954年,靳予贵在其所绘地质图中标出“复理石式沉积”。1957年,张尔道在其发表的文章中也指出“地层是一套具有复理式结构的轻微变质岩系”。1961年,孔凡宗在其所编1:20万凤县幅地质图说明书中进一步强调是复理石建造。最近,李继亮等从理论上作了高度的概括,并提到
SPICE MODEL FOR LDD STRUCTURE CMOS DEVICE AT 35K
35KCMOS器件LDD结构的SPICE宏模型

LIU Wen-Yong,DING Rui-Jun,FENG Qi,
刘文永
,丁瑞军,冯琪

红外与毫米波学报 , 2008,
Abstract: 针对BSIM3v3模型在35K低温下无法模拟LDD(轻掺杂漏区)所引起的串联电阻异常,提出了可以模拟这一异常的SPICE宏模型.通过修改CMOS器件常温BSIM3v3模型中的一些与温度有关的参数值,得到35K BSIM3v3模型.模拟结果表明,根据此模型进行参数提取后的Ⅰ-Ⅴ特性曲线与实测曲线十分吻合.最后,运用此模型对CMOS传输门和两级运算放大器进行仿真,结果表明LDD串联电阻效应对这些电路产生了重要影响,该模型明显提高了低温BSIM3v3的仿真精度.
Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process
王 源,贾 嵩,陈中建,吉利久
中国物理 B , 2006,
Abstract: A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.
Emerging Challenges in ESD Protection for RF ICs in CMOS
CMOS射频集成电路ESD保护的挑战

Wang Albert,Lin Lin,Wang Xin,Liu Hainan,Zhou Yumei,
王自惠
,林琳,王昕,刘海南,周玉梅

半导体学报 , 2008,
Abstract: On-chip electrostatic discharge (ESD) protection design has become an emerging challenge for radio-frequency (RF) integrated circuits (IC) design as IC technologies migrate into the very-deep-sub-micron (VDSM) regime and RF ICs move into multi-GHz operations.The key problem originates from the complex interaction between the ESD protection circuitry and the core RF IC circuit under protection.This paper discusses the recent development in RF ESD protection research and design,outlining emerging challenges,new design methods,and novel RF ESD protection solutions.
A Novel ESD Protection Circuit Based on a CMOS Process
一种基于CMOS工艺的新型结构ESD保护电路

Zhang Bing,Chai Changchun,Yang Yintang,
张冰
,柴常春,杨银堂

半导体学报 , 2008,
Abstract: 根据全芯片静电放电(ESD)损伤防护理论,设计了一种新型结构保护电路,采用0.6μm 标准CMOS p阱工艺进行了新型保护电路的多项目晶圆(MPW)投片验证. 通过对同一MPW中的新型结构ESD保护电路和具有同样宽长比的传统栅极接地MOS(GG-nMOS)保护电路的传输线脉冲测试,结果表明在不增加额外工艺步骤的前提下,本文设计的新型结构ESD保护电路芯片面积减少了约22%,静态电流更低,而抗ESD电压提高了近32%. 该保护电路通过了5kV的人体模型测试.
A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs  [PDF]
Jin Young Choi, Choongkoo Park
Circuits and Systems (CS) , 2011, DOI: 10.4236/cs.2011.23025
Abstract: We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device. The comparison study mainly focuses on robustness against the HBM ESD in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.
0.8μm CMOS LDD器件可靠性实验和分析
余山,章定康,黄敞
电子与信息学报 , 1994,
Abstract: 针对实验中发现的亚微米LDD结构的特殊的衬底电流现象和退化现象,进行了二维器件数值模拟,解释了LDD器件退化的原因,最后提出了LDD器件的优化工艺条件。
Asymmetry LDD MOSFET
非对称轻掺杂漏(LDD)MOSFET

CHEN Xueliang/,
陈学良
,王自惠

半导体学报 , 1990,
Abstract: A new MOSFET structure-Asymmetry LDD MOSFET,which contains only a lightlydoped buffer region near the drain, has been proposed and fabricated.Asymmetry LDD structure can decrease source-drain series resistance and improve transconductance as comparedwith the conventional LDD MOSFET, keeping the same capability of reducing hot-carrier effects.CMOS ICs consisting of the asymmetry LDD devices exhibit a better performance inspeed.
Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS
5V CMOS中GGNMOS ESD失效电流和沟道长度正向关系的分析

Wu Daoxun,Jiang Lingli,Fan Hang,Fang Jian,Zhang Bo,
吴道训
,蒋苓利,樊航,方健,张波

半导体学报 , 2013,
Abstract: Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET (GGNMOS) was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse (TLP) measurements and Sentaurus technology computer aided design (TCAD) 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.
Design on an ESD Protection Circuit with GG-NMOS Structure in CMOS Technology
CMOS工艺中GG-NMOS结构ESD保护电路设计

Du Ming,Hao Yue,Zhu Zhiwei,
杜鸣
,郝跃,朱志炜

半导体学报 , 2005,
Abstract: An ESD protection circuit which uses a GG-NMOS structure is presented.The operating principle and test results are depicted.An improved project,gate-couple technology,on the circuit is presented,and the anticipated effect is achieved.The ability of the circuit achieves class 2 of the human-body model.It is also indicated that ESD induces damage of the gate oxide with microcosmic mechanisms,where ESD occurs based on simulation.
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