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ESD and Its Related Mechanisms on LDD-CMOS
LDD-CMOS中ESD及其相关机理

Ma Wei,Hao Yue,
马巍
,郝跃

半导体学报 , 2003,
Abstract: LDD is widely used in sub half micrometer CMOS VLSI.Due to its improvement of the distribution of electrical field in channel,the effect of high field near the drain is reduced.Consequently,the life of hot carrier of the circuits and devices is prolonged in the aspect of reliability.However,LDD has a poor performance against ESD stress.A research has been made on the latent damages under the influences of snapback.And special attention is given to the correlation with hot carrier in LDD gg nMOS during ESD events.
ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR
内嵌SCR的LDMOS器件双骤回ESD特性研究

Jiang Lingli,Zhang Bo,Fan Hang,Qiao Ming,Li Zhaoji,
蒋苓利
,张波,樊航,乔明,李肇基

半导体学报 , 2011,
Abstract: Criterion for the second snapback of LDMOS with embedded SCR is given in this letter based on parasitic parameter analysis. According to this criterion, three typical structures are compared by numerical simulation, and structure parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experiment data showed that, as second snapback voltage decreased from 25.4V to 8.1V, the discharge ability of optimized structure raised from 0.57A up to 3.1A.
两微米外延N阱CMOS艺的研究
马槐楠,徐葭生
半导体学报 , 1987,
Abstract: 本文描述2μm外延N阱CMOS工艺的研究,在工艺模拟和实验的基础上制定了合理的、可行的工艺流程.在工艺中成功地应用了全离子注入和红外瞬态退火技术.实验结果表明,2μm CMOS 器件具有优良的特性,适合超大规模集成电路的要求.5伏工作电压,21级2μmCMOS反相器环振链的级延时是0.48ns,每级的延时功耗乘积是0.49pJ.P~-/P~+外延层结合N阱伪集电极保护环,可在CMOS电路中最易产生Latch-up的I/O电路部分保证不发生Latch-up.本工艺可以应用于超大规模集成电路的制作.
Design on an ESD Protection Circuit with GG-NMOS Structure in CMOS Technology
CMOS工艺中GG-NMOS结构ESD保护电路设计

Du Ming,Hao Yue,Zhu Zhiwei,
杜鸣
,郝跃,朱志炜

半导体学报 , 2005,
Abstract: An ESD protection circuit which uses a GG-NMOS structure is presented.The operating principle and test results are depicted.An improved project,gate-couple technology,on the circuit is presented,and the anticipated effect is achieved.The ability of the circuit achieves class 2 of the human-body model.It is also indicated that ESD induces damage of the gate oxide with microcosmic mechanisms,where ESD occurs based on simulation.
Influence of HALO and Source/Drain Implantation Variations on Threshold Voltage in 45nm CMOS Technology  [cached]
Fauziyah Salehuddin,Ibrahim Ahmad,Fazrena Azlee Hamid,Azami Zaharim
International Journal of Electronics, Computer and Communications Technologies , 2012,
Abstract: In this paper, we investigate the influence of process parameters such as HALO and Source/Drain (S/D) Implantation on threshold voltage (VTH) in Complementary Metal Oxide Semiconductor (CMOS) technology using Taguchi Method. The level of importance of the process parameters on VTH were determined by using analysis of variance. The fabrication of the transistor device was performed by using fabrication simulator of ATHENA. The electrical characterization of the device was implemented by using electrical characterization simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing the process parameters. The other two process parameters in this research are oxide growth temperature and silicide anneal temperature. Whereas, the two noise factors are sacrificial oxide temperature and annealing process temperature. Each of the noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. In NMOS and PMOS devices, the major factor affecting the threshold voltage was HALO (70%) and oxide growth temperature (45%) respectively. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.150V and +0.150V respectively.
Linearity Improvement of Cascode Cmos Lna Using a Diode Connected Nmos Transistor with a Parallel RC Circuit
Chieh-Pin Chang;Wei-Chih Chien;Chun-Chi Su;Yeong-Her Wang;Ja-Hao Chen
PIER C , 2010, DOI: 10.2528/PIERC10082411
Abstract: A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6 mA from a 1.8 V power supply.
A Novel CMOS Voltage Reference Based on Threshold Voltage Difference Between p-Type and n-Type MOSFETs
一种新型的基于pMOS和nMOS阈值电压差的CMOS电压基准源

Kong Ming,Guo Jianmin,Zhang Ke,Li Wenhong,
孔明
,郭健民,张科,李文宏

半导体学报 , 2007,
Abstract: 提出了一种新的纯MOS结构的基准电压源,它利用pMOS和nMOS的阈值电压差来抵消工艺偏差,提高了基准的精度.该电路经过Chartered 0.35mm标准CMOS工艺成功流片,芯片面积为0.022mm2.测试结果表明:输出平均电压在室温下与仿真结果的绝对误差为6mV,在0~100℃范围内温度系数为180ppm/℃,电源调整率为±1.1%.该基准应用于自适应功率管驱动器中.
Off-State Breakdown Characteristics of Body-Tied Partial-Depleted SOI nMOS Devices
Wu Junfeng,Zhong Xinghua,Li Duoli,Kang Xiaohui,Shao Hongxu,YANG Jianjun,Hai Chaohe,Han Zhengsheng,
Wu Junfeng
,Zhong Xinghu,Li Duoli,Kang Xiaohui,Shao Hongxu,Yang Jianjun,Hai Chaohe,and Han Zhengsheng

半导体学报 , 2005,
Abstract: Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.
Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits  [PDF]
Ashok Babu Ch, J. V. R. Ravindra, K. Lalkishore
Circuits and Systems (CS) , 2015, DOI: 10.4236/cs.2015.63007
Abstract: CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling methods, but in conventional CMOS devices in ultra deep submicron technology, leakage power becomes the major portion apart of dynamic power. The demerits of the conventional CMOS is less speed and, more leakage, for any digital design PDP is the figure of merit which can be used to determine energy consumed per switching event, hence we designed a NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.
Gate-enclosed NMOS transistors
基于封闭形栅NMOS晶体管的研究

Fan Xue,Li Ping,Li Wei,Zhang Bin,Xie Xiaodong,Wang Gang,Hu Bin,Zhai Yahong,
范雪
,李平,李威,张斌,谢小东,王刚,胡滨,翟亚红

半导体学报 , 2011,
Abstract: 封闭形栅的NMOS晶体管广泛应用于总剂量辐射效应加固的电路中。为了定量比较不同的封闭形栅晶体管的性能以及设计代价,在0.35μm 商业CMOS工艺上设计制造了标准条栅和两种封闭形栅(包括环栅和半环栅)的NMOS晶体管。通过对比这三种器件的最小宽长比、晶体管面积,得出环栅与半环栅的版图形式带来的面积牺牲与设计的晶体管宽长比密切相关。并通过对这三种器件的输出特性和转移特性的对比测试,分析了常见的封闭形栅的有效宽长比提取方法,结果表明对于环栅NMOS,“中线近似”可能带来10%的误差,而商业工艺线提供的宽长比提取方法由于是针对条形栅,在设计中需要经过修正才能适用于封闭形栅的晶体管设计。对于半环栅NMOS,我们提出了一种简略的宽长比估算方法, 实验结果显示其误差小于8%。
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