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Optimization of FRM FIR Digital Filters Over CSD and CDBNS Multiplier Coefficient Spaces Employing a Novel Genetic Algorithm  [cached]
Patrick Mercier,Sai Mohan Kilambi,Behrouz Nowrouzian
Journal of Computers , 2007, DOI: 10.4304/jcp.2.7.20-31
Abstract: It is well known that frequency response masking (FRM) FIR digital filters can be designed to exhibit very sharp-transition bands at the cost of slightly larger filter lengths as compared to the conventional FIR digital filters. The FRM FIR digital filters permit efficient hardware implementations due to an inherently large number of zerovalued multiplier coefficients in their transfer functions. The hardware complexity of these FIR digital filters can be further reduced by employing computationally efficient number systems for the representation of the constituent non-zero-valued multiplier coefficients. This paper presents a novel genetic algorithm for the design and discrete optimization of FRM FIR digital filters over the conventional canonical signed-digit (CSD) as well as the emerging double base number system (DBNS) multiplier coefficient spaces. This genetic algorithm is based on a pair of indexed look-up tables (LUTs) of permissible CSD/DBNS numbers whose indices form a closed set under the genetic algorithm operations of crossover and mutation. The CSD/DBNS values themselves permit pre-specified word-lengths and pre-specified number of non-zero bits. The salient feature of the proposed genetic algorithm is that it automatically leads to legitimate CSD/DBNS multiplier coefficients without any recourse to gene repair during optimization. The main features of the proposed genetic algorithm are demonstrated through its application to the design of a pair of low-pass and band-pass FRM FIR digital filters.
High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier  [PDF]
S. Jayakumar, Dr. A. Sumathi
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.711312
Abstract: In this, todays world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay; area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.
Computationally Efficient Multiplier-Free Fir Filter Design
Jovanovic Dolecek, Gordana;Mitra, Sanjit K.;
Computación y Sistemas , 2007,
Abstract: this paper presents a very simple multiplier-free finite impulse response (fir) lowpass filter design procedure. it involves approximation of an equiripple fir by rounding operation and application of the sharpening technique. in that way the overall filter is based on combining one simple filter with integer coefficients. the parameters of the design are the rounding constant and the parameters of the sharpening polynomials such as the order of tangencies m and l. our analysis indicates that utilizing this approach the required number of total nonzero bits becomes quite low and less than in the minimum number of signed powers-of-two (mnspt) design. the cost is the increase of the total numbers of sums and the delays.
Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter  [PDF]
S. Chinnapparaj, D. Somasundareswari
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.79213
Abstract: Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response(FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.
Novel Approach of Designing Multiplier-less Finite Impulse Response Filter using Differential Evolution Algorithm
Abhijit Chandra,Sudipta Chattopadhyay
International Journal of Intelligent Systems and Applications , 2012,
Abstract: Reduction of computational complexity of digital hardware has drawn the special attention of researchers in recent past. Proper emphasis is needed in this regard towards the settlement of computationally efficient as well as functionally competent design of digital systems. In this communication, we have made one novel attempt for designing multiplier-free Finite duration Impulse Response (FIR) digital filter using one robust evolutionary optimization technique, called Differential Evolution (DE). The search has been directed through two sequentially opposite paths which include quantization and optimization as fundamental operations. Besides performing a detailed comparative analysis between these two proposed approaches; the performance evaluation of the designed filter with other existing discrete coefficient FIR models has also been carried out. Finally, the optimum search method for realizing the required set of specifications has been suggested.
S. Prem Kumar,S. Sivaprakasam,,G. Damodharan,,V. Ellappan
International Journal on Computer Science and Engineering , 2011,
Abstract: In this paper we proposed a three stage pipelined finite-impulse response (FIR) filter, this FIR filter contains multipliers such as Hybrid multiplier, Booth multiplier algorithm and Array multiplier. In general, multiplication process consists of two parts as multiplicand and multiplier. According to the array multiplier, the numbers of partial products (PP) are equal to the number of bits in multiplier. Booth multiplier is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Booth's algorithm can be reduced by half using booth recoding. But in the hybrid multiplication technique, the partial products can still be reduced which in turn reduces the switching activity and power consumption. Multiplication is a very important operation in many digital signal processing (DSP) applications. In our proposed system, the performance of our hybrid multiplier is compared with an array multiplier and booth multiplier. The comparison is based on synthesis results obtained by synthesizing the multiplier architectures targeting a Xilinx FPGA.
International Journal of Innovative Research in Computer and Communication Engineering , 2013,
Abstract: In this paper, we present a new efficient distributed arithmetic (NEDA) formulation of the computation of 1-D discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit parallel for high-speed and low hardware implementations, respectively. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. The bit-parallel structure has 100% hardware utilization efficiency. Compared with the existing multiplier-less structures, the proposed structures offer significantly higher throughput rate and involve less area-delay product.
Reducting Power Dissipation in Fir Filter: an Analysis  [cached]
Rakesh Kumar Bansal,Manoj Garg,Savina Bansal
Signal Processing : An International Journal , 2010,
Abstract: In this paper, three existing techniques, Signed Power-of-Two (SPT), Steepest decent and Coefficient segmentation, for power reduction of FIR filters are analyzed. These techniques reduce switching activity which is directly related to the power consumption of a circuit. In an FIR filter, the multiplier consumes maximum power. Therefore, power consumption can be reduced either by by making the filter multiplier-less or by minimizing hamming distance between the coefficients of this multiplier as it directly translates into reduction in power dissipation [8]. The results obtained on four filters (LP) show that hamming distance can be reduced upto 26% and 47% in steepest decent and coefficient segmentation algorithm respectively. Multiplier-less filter can be realized by realizing coefficients in signed power-of-two terms, i.e. by shifting and adding the coefficients, though at the cost of shift operation overhead.
The Harmony Platform  [PDF]
Jean-Rémy Falleri,Cédric Teyton,Matthieu Foucault,Marc Palyart,Floréal Morandat,Xavier Blanc
Computer Science , 2013,
Abstract: According to Wikipedia, The Mining Software Repositories (MSR) field analyzes the rich data available in software repositories, such as version control repositories, mailing list archives, bug tracking systems, issue tracking systems, etc. to uncover interesting and actionable information about software systems, projects and software engineering. The MSR field has received a great deal of attention and has now its own research conference : http://www.msrconf.org/. However performing MSR studies is still a technical challenge. Indeed, data sources (such as version control system or bug tracking systems) are highly heterogeneous. Moreover performing a study on a lot of data sources is very expensive in terms of execution time. Surprisingly, there are not so many tools able to help researchers in their MSR quests. This is why we created the Harmony platform, as a mean to assist researchers in performing MSR studies.
Design of Low Power and Area Efficient Architecture for Reconfigurable FIR Filter  [PDF]
International Journal of Recent Technology and Engineering , 2013,
Abstract: Finite Impulse Response (FIR) filters are widely applied in multi-standard wireless communications. These filters provide linear phase and absolute stability. The FIR offers a low sensitivity for the coefficient quantization errors. These properties increase the usage of FIR filter. In this paper, reconfigurable digital filter architecture is proposed. The approach is well suited if the filter order is fixed. The filter is dynamically reconfigured by changing the filter order. The order is changed by turning of the multiplier whose inputs are mitigate to be eliminated. The complexity of linear phase FIR filters is dominated by the number of adders (sub-tractors) in the coefficient multiplier. The Common Sub-expression Elimination (CSE) algorithm reduces number of adders in the multipliers and dynamically reconfigurable filters can be efficiently implemented. The proposed filter architectures offers power and area reduction over the existing FIR filter implementation.
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