Motion estimation is the most important module in H.264 video encoding algorithm since it offer the best compression ratio compared to intra prediction and entropy encoding. However, using the allowed features for inter prediction such as variable block size matching, multi-reference frames and fractional pel search needs a lot of computation cycles. For this purpose, we propose in this paper an Application Specific Instruction-set Processor (ASIP) solution for implementing inter prediction. An exhaustive full and fractional pel combined with variable block size matching search are used. The solution, implemented in FPGA, offers both performance and flexibility to the user to reconfigure the search algorithm.
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I. Werda and F. Kossentini, “Analysis and Optimization of UB Video’s H.264 Baseline Encoder if Texas Instrument’s TMS320DM642 DSP,” IEEE International Conference on Image Processing, Atlanta, October 2006.
W. Geurts, et al., “Design of Application-Specific Instruction-Set Processors for Multi-Media, Using a Retargetable Compilation Flow,” Proceedings of Global Signal Processing (GSPx) Conference, Target Compiler Technologies, Santa Clara, 2005.
M. A. Benayed, A. Samet and N. Masmoudi, “SAD Implementation and Optimization for H.264/AVC Encoder on TMS320C64 DSP,” 4th International Conference on Sciences of Electronic, Technologies of Information and Telecommunications(SETIT 2007), Tunisia, 25-29 March 2007.