A domain extension algorithm to correct the comparator
offsets of pipeline analog-to-digital converters (ADCs) is presented, in which
the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain.
This algorithm is designed for high speed and low comparator accuracy
application. The comparator offset correction ability is improved. This new
approach also promises significant improvements to the spurious-free
dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise
ratio (SNR) and the minor analog and digital circuit modifications. Behavioral
simulation results are presented to demonstrate the effectiveness of the
algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and
30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for
a 10-bit pipeline ADC.
B. Peng, H. Li, P. Lin and Y. Chiu, “An Offset Double Conversion Technique for Digital Calibration of Pipelin ed ADCs,” IEEE Transactions on Circuits and SystemsII: Express Briefs, Vol. 57, No. 12, 2010, pp. 961965.
C. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen and B. Nikolic, “Background ADC Calibra tion in Digital Domain,” Proceedings of IEEE Custom Integrated Circuits Conference, San Jose, 2124 Septem ber 2008, pp. 301304.
Y. Chiu, C. W. Tsang, B. Nikolic and P. R. Gray, “Least Mean Square Adaptive Digital Background Calibration of Pipelined AnalogToDigital Converters,” IEEE Transac tions on Circuits and Systems I: Regular Papers, Vol. 51, No. 1, 2004, pp. 3846. http://dx.doi.org/10.1109/TCSI.2003.821306
W. Liu, P. Huang and Y. Chiu, “A 12b 22.5/45MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC Achieving over 90 dB SFDR,” Proceedings of IEEE ISSCC Digest of Technical Papers, San Francisco, 711 February 2010, pp. 380382.
J. McNeill, M. C. W. Coln and B. J. Larivee, “‘Split ADC’ Architecture for Deterministic Digital Background Cali bration of a 16Bit 1MS/s ADC,” IEEE Journal of Solid State Circuits, Vol. 40, No. 12, 2005, pp. 24372445. http://dx.doi.org/10.1109/JSSC.2005.856291
J. Li and U.K. Moon, “Background Calibration Tech niques for Multistage Pipelined ADC’s with Digital Re dundancy,” IEEE Transactions on Circuits and Systems II, Analog & Digital Signal Processing, Vol. 50, No. 9, 2003, pp. 531538.
J. A. McNeill, S. Goluguri and A. Nair, “‘Split ADC’ Di gital Background Correction of OpenLoop Residue Am plifier Nonlinearity Errors in a 14b Pipeline ADC,” Pro ceedings of IEEE ISCAS, New Orleans, 2730 May 2007, pp. 12371240.
M. TaherzadehSani and A. A. Hamoui, “Digital Background Calibration of a 0.4pJ/step 10Bit Pipelined ADC without PN Generator in 90nm Digital CMOS,” Proceedings of IEEE Asian SolidState Circuits Conference, Fukuoka, 35 November 2008, pp. 5356.
J. P. Keane, P. J. Hurst and S. H. Lewis, “Background Interstage Gain Calibration Technique for Pipelined ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 52, No. 1, 2005, pp. 3243. http://dx.doi.org/10.1109/TCSI.2004.839534
S. Yang, J. Cheng and P. Wang, “VariableAmplitude DitherBased Digital Background Calibration Algorithm for Linear and HighOrder Nonlinear Error in Pipelined ADCs,” Microelectronics Journal, Vol. 41, No. 7, 2010, pp. 403410. http://dx.doi.org/10.1016/j.mejo.2010.04.012
S. Hamami, L. Fleshel and O. YadidPecht, “CMOS Image Sensor Employing 3.3V 12 Bit 6.3 MS/s Pipelined ADC,” Sensors and Actuators, Vol. 135, No. 1, 2007, pp. 119125. http://dx.doi.org/10.1016/j.sna.2006.06.041