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A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology

DOI: 10.1155/2013/905686

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A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case. 1. Introduction Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems. An NMOSFET has been the most popular ESD protection candidate for a long time. Since the shrinking of device size advances continually, the ESD capability of the NMOS device encounters more challenges [1–7]. A gate-grounded NMOS (GGNMOS) can no longer satisfy the ESD protection mission easily. ESD NMOS protection devices usually need the large width size to deal with ESD events. This results in multifinger layout style which is commonly used in practical IC I/O area. But it also has a critical drawback which is not favorable for the ESD protection requirement. The conduction current is usually unevenly distributed along the width direction of the multifingers. Gate-coupling technique using the property that increases the gate bias can reduce the first trigger point of the NMOS device and enable uniform ESD current distribution [4, 8, 9]. Although gate-coupling technique can improve the ESD capability, it still has gate overdriven effect if the gate voltage coupled is much larger than its threshold voltage, and this leads to serious ESD degradation. Furthermore, inserted or butting substrate pickups in the source diffusion region of the ESD NMOS device in deep submicrometer technology also degraded ESD reliability seriously. Such layout style has been strictly prohibited in practical ESD design applications by the technology design rules. Therefore, in this work, a new substrate-and-gate triggering (SGT) structure that utilizes dynamic

References

[1]  A. Amerasekera and C. Duvvury, “The impact of technology scaling on ESD robustness and protection circuit design,” in Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, pp. 237–245, Las Vegas, Nev, USA, September 1994.
[2]  D. L. Lin, “ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown,” in Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, pp. 73–81, Lake Vista, Fla, USA, September 1993.
[3]  C. Duvvury, R. N. Rountree, D. Baglee, and R. McPhee, “ESD protection reliability in 1?μM CMOS technologies,” in Proceedings of the 24th Annual IEEE International Reliability Physics Symposium (IRPS '86), pp. 199–205, Anaheim, Calif, USA, April 1986.
[4]  C. Duvvury and C. Diaz, “Dynamic gate coupling of NMOS for efficient output ESD protection,” in Proceedings of the 30th Annual IEEE International Reliability Physics Symposium (IRPS '92), pp. 141–150, San Diego, Calif, USA, April 1992.
[5]  K. H. Oh, C. Duvvury, K. Banerjee, and R. W. Dutton, “Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors,” IEEE Transactions on Electron Devices, vol. 49, no. 12, pp. 2171–2182, 2002.
[6]  T. L. Polgreen and A. Chatterjee, “Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow,” IEEE Transactions on Electron Devices, vol. 39, no. 2, pp. 379–388, February 1992.
[7]  C. Y. Huang and K. S. Tseng, “Analysis of ESD current nonuniformity in a multi-finger NMOS device,” Journal of Ching-Yun University, vol. 26, no. 2, pp. 55–66, September 2006.
[8]  A. Amerasekera, C. Duvvury, V. Reddy, and M. Rodder, “Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '95), pp. 547–550, Washington, DC, USA, December 1995.
[9]  K. H. Oh, C. Duvvury, K. Banerjee, and R. W. Dutton, “Gate bias induced heating effect and implications for the design of deep submicron ESD protection,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '01), pp. 14.2.1–14.2.4, Washington, DC, USA, December 2001.
[10]  F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. M. Hu, “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Transactions on Electron Devices, vol. 44, no. 3, pp. 414–422, March 1997.
[11]  S. Voldman, F. Assaderaghi, J. Mandelman, L. Hsu, and G. Shahidi, “Dynamic threshold body- and gate-coupled SOI ESD protection networks,” in Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, pp. 210–220, Orlando, Fla, USA, September 1997.
[12]  M. D. Ker, T. Y. Chen, and C. Y. Wu, “Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique,” in Proceedings of the 10th Annual IEEE International ASIC Conference and Exhibit, pp. 287–290, Portland, Ore, USA, September 1997.

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